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Message-Id: <20250409152558.1007335-2-arkadiusz.kubalewski@intel.com>
Date: Wed, 9 Apr 2025 17:25:55 +0200
From: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
To: donald.hunter@...il.com,
kuba@...nel.org,
davem@...emloft.net,
edumazet@...gle.com,
pabeni@...hat.com,
horms@...nel.org,
vadim.fedorenko@...ux.dev,
jiri@...nulli.us,
anthony.l.nguyen@...el.com,
przemyslaw.kitszel@...el.com,
andrew+netdev@...n.ch,
saeedm@...dia.com,
leon@...nel.org,
tariqt@...dia.com,
jonathan.lemon@...il.com,
richardcochran@...il.com,
aleksandr.loktionov@...el.com,
milena.olech@...el.com
Cc: netdev@...r.kernel.org,
linux-kernel@...r.kernel.org,
intel-wired-lan@...ts.osuosl.org,
linux-rdma@...r.kernel.org,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
Subject: [PATCH net-next v1 1/4] dpll: add features and capabilities to dpll device spec
Add infrastructure for adding simple control over dpll device level
features.
Add define for new dpll device level feature:
DPLL_FEATURES_ALL_INPUTS_PHASE_OFFSET_MONITOR - control over monitoring of
all input pins phase offsets.
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@...el.com>
Reviewed-by: Milena Olech <milena.olech@...el.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
---
Documentation/netlink/specs/dpll.yaml | 25 +++++++++++++++++++++++++
drivers/dpll/dpll_nl.c | 5 +++--
include/uapi/linux/dpll.h | 13 +++++++++++++
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 8feefeae5376..c9a3873e03f6 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -240,6 +240,18 @@ definitions:
integer part of a measured phase offset value.
Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
fractional part of a measured phase offset value.
+ -
+ type: flags
+ name: features
+ doc: |
+ Allow simple control (enable/disable) and status checking over features
+ available per single dpll device.
+ entries:
+ -
+ name: all-inputs-phase-offset-monitor
+ doc: |
+ select if phase offset values are measured and reported for
+ all the input pins available for given dpll device
attribute-sets:
-
@@ -293,6 +305,16 @@ attribute-sets:
be put to message multiple times to indicate possible parallel
quality levels (e.g. one specified by ITU option 1 and another
one specified by option 2).
+ -
+ name: capabilities
+ type: u32
+ enum: features
+ doc: Features available for a dpll device.
+ -
+ name: features
+ type: u32
+ enum: features
+ doc: Features enabled for a dpll device.
-
name: pin
enum-name: dpll_a_pin
@@ -483,6 +505,8 @@ operations:
- temp
- clock-id
- type
+ - capabilities
+ - features
dump:
reply: *dev-attrs
@@ -499,6 +523,7 @@ operations:
request:
attributes:
- id
+ - features
-
name: device-create-ntf
doc: Notification about device appearing
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index fe9b6893d261..3712a693c458 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -37,8 +37,9 @@ static const struct nla_policy dpll_device_get_nl_policy[DPLL_A_ID + 1] = {
};
/* DPLL_CMD_DEVICE_SET - do */
-static const struct nla_policy dpll_device_set_nl_policy[DPLL_A_ID + 1] = {
+static const struct nla_policy dpll_device_set_nl_policy[DPLL_A_FEATURES + 1] = {
[DPLL_A_ID] = { .type = NLA_U32, },
+ [DPLL_A_FEATURES] = NLA_POLICY_MASK(NLA_U32, 0x1),
};
/* DPLL_CMD_PIN_ID_GET - do */
@@ -105,7 +106,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
.doit = dpll_nl_device_set_doit,
.post_doit = dpll_post_doit,
.policy = dpll_device_set_nl_policy,
- .maxattr = DPLL_A_ID,
+ .maxattr = DPLL_A_FEATURES,
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
},
{
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index bf97d4b6d51f..7c8e929831aa 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -192,6 +192,17 @@ enum dpll_pin_capabilities {
#define DPLL_PHASE_OFFSET_DIVIDER 1000
+/**
+ * enum dpll_features - Allow simple control (enable/disable) and status
+ * checking over features available per single dpll device.
+ * @DPLL_FEATURES_ALL_INPUTS_PHASE_OFFSET_MONITOR: select if phase offset
+ * values are measured and reported for all the input pins available for
+ * given dpll device
+ */
+enum dpll_features {
+ DPLL_FEATURES_ALL_INPUTS_PHASE_OFFSET_MONITOR = 1,
+};
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -204,6 +215,8 @@ enum dpll_a {
DPLL_A_TYPE,
DPLL_A_LOCK_STATUS_ERROR,
DPLL_A_CLOCK_QUALITY_LEVEL,
+ DPLL_A_CAPABILITIES,
+ DPLL_A_FEATURES,
__DPLL_A_MAX,
DPLL_A_MAX = (__DPLL_A_MAX - 1)
--
2.38.1
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