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Message-ID: <20250414163640.548aa37b@kernel.org>
Date: Mon, 14 Apr 2025 16:36:40 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: Andrew Lunn <andrew+netdev@...n.ch>, Heiner Kallweit
<hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>
Cc: Christian Marangi <ansuelsmth@...il.com>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Paolo Abeni
<pabeni@...hat.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Florian Fainelli
<florian.fainelli@...adcom.com>, Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>, Marek BehĂșn
<kabel@...nel.org>, Andrei Botila <andrei.botila@....nxp.com>, Sabrina
Dubroca <sd@...asysnail.net>, Eric Woudstra <ericwouds@...il.com>, Daniel
Golle <daniel@...rotopia.org>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.or
Subject: Re: [net-next PATCH v7 5/6] net: phy: Add support for Aeonsemi
AS21xxx PHYs
On Thu, 10 Apr 2025 11:53:35 +0200 Christian Marangi wrote:
> Add support for Aeonsemi AS21xxx 10G C45 PHYs. These PHYs integrate
> an IPC to setup some configuration and require special handling to
> sync with the parity bit. The parity bit is a way the IPC use to
> follow correct order of command sent.
>
> Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1,
> AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1,
> AS21210PB1 that all register with the PHY ID 0x7500 0x7510
> before the firmware is loaded.
>
> They all support up to 5 LEDs with various HW mode supported.
>
> While implementing it was found some strange coincidence with using the
> same logic for implementing C22 in MMD regs in Broadcom PHYs.
>
> For reference here the AS21xxx PHY name logic:
Would any of the PHY maintainers be willing to cast their review tag
upon this patch? :)
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