netdev - [PATCH 13/13] ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950

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Message-Id: <20250416-wmt-updates-v1-13-f9af689cdfc2@gmail.com>
Date: Wed, 16 Apr 2025 12:21:38 +0400
From: Alexey Charkov <alchark@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, 
 Andi Shyti <andi.shyti@...nel.org>, Rob Herring <robh@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Ulf Hansson <ulf.hansson@...aro.org>, Andrew Lunn <andrew+netdev@...n.ch>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Uwe Kleine-König <ukleinek@...nel.org>, 
 Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-i2c@...r.kernel.org, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-mmc@...r.kernel.org, netdev@...r.kernel.org, 
 linux-pwm@...r.kernel.org, Alexey Charkov <alchark@...il.com>
Subject: [PATCH 13/13] ARM: dts: vt8500: Add L2 cache controller on
 WM8850/WM8950

WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its
L2 cache, add it.

The parameters have been deduced from vendor's U-boot environment
variables, which the downstream code uses to initialize the
controller. They set the following register values:

aux = 0x3e440000
prefetch_ctrl = 0x70000007

Their initialization code also unconditionally sets the flags
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too

Signed-off-by: Alexey Charkov <alchark@...il.com>
---
 arch/arm/boot/dts/vt8500/wm8850.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi
index 55de8d439688c5710d1e9a37890bbd274895be42..f2fb2e0b04c31dbdf320387f24c3b09d231d90b8 100644
--- a/arch/arm/boot/dts/vt8500/wm8850.dtsi
+++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi
@@ -18,6 +18,7 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x0>;
+			next-level-cache = <&l2_cache>;
 		};
 	};

@@ -35,6 +36,19 @@ soc {
 		ranges;
 		interrupt-parent = <&intc0>;

+		l2_cache: cache-controller@...00000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xd9000000 0x1000>;
+			arm,double-linefill = <1>;
+			arm,dynamic-clock-gating = <1>;
+			arm,shared-override;
+			arm,standby-mode = <1>;
+			cache-level = <2>;
+			cache-unified;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
+		};
+
 		intc0: interrupt-controller@...40000 {
 			compatible = "via,vt8500-intc";
 			interrupt-controller;

-- 
2.49.0