netdev - [PATCH v5 0/5] clk: sophgo: add SG2044 clock controller support

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Message-ID: <20250418020325.421257-1-inochiama@gmail.com>
Date: Fri, 18 Apr 2025 10:03:19 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Inochi Amaoto <inochiama@...il.com>,
	Richard Cochran <richardcochran@...il.com>,
	Vinod Koul <vkoul@...nel.org>,
	Alexander Sverdlin <alexander.sverdlin@...il.com>,
	Nikita Shubin <nikita.shubin@...uefel.me>,
	Linus Walleij <linus.walleij@...aro.org>,
	Arnd Bergmann <arnd@...db.de>
Cc: linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	sophgo@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org,
	Yixun Lan <dlan@...too.org>,
	Longbin Li <looong.bin@...il.com>
Subject: [PATCH v5 0/5] clk: sophgo: add SG2044 clock controller support

The clock controller of SG2044 provides multiple clocks for various
IPs on the SoC, including PLL, mux, div and gates. As the PLL and
div have obvious changed and do not fit the framework of SG2042,
a new implement is provided to handle these.

Changed from v4:
1. patch 1,3: Applied Krzysztof's tag.
2. patch 1: fix header path in description.
3. patch 4: drop duplicated module alias.
4. patch 5: make sg2044_clk_desc_data const.

Changed from v3:
- https://lore.kernel.org/all/20250226232320.93791-1-inochiama@gmail.com
1. patch 1,2: Add top syscon binding and aux driver.
2. patch 4: Separate the syscon pll driver to a standalone one.
3. patch 4: use abs_diff to compare pll clock.
4. patch 4: remove unnecessary else.
5. patch 5: use clk_hw for parent clocks if possible.
6. patch 5: inline the header which is necessary.
7. patch 5: make common array as const.

Changed from v2:
- https://lore.kernel.org/all/20250204084439.1602440-1-inochiama@gmail.com/
1. Applied Chen Wang's tag.
2. patch 2: fix author mail infomation.

Changed from v1:
- https://lore.kernel.org/all/20241209082132.752775-1-inochiama@gmail.com/
1. patch 1: Applied Krzysztof's tag.
2. patch 2: Fix the build warning from bot.

Inochi Amaoto (5):
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  soc: sophgo: sg2044: Add support for SG2044 TOP syscon device
  dt-bindings: clock: sophgo: add clock controller for SG2044
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  clk: sophgo: Add clock controller support for SG2044 SoC

 .../bindings/clock/sophgo,sg2044-clk.yaml     |   99 +
 .../soc/sophgo/sophgo,sg2044-top-syscon.yaml  |   49 +
 drivers/clk/sophgo/Kconfig                    |   19 +
 drivers/clk/sophgo/Makefile                   |    2 +
 drivers/clk/sophgo/clk-sg2044-pll.c           |  628 ++++++
 drivers/clk/sophgo/clk-sg2044.c               | 1812 +++++++++++++++++
 drivers/soc/Kconfig                           |    1 +
 drivers/soc/Makefile                          |    1 +
 drivers/soc/sophgo/Kconfig                    |   21 +
 drivers/soc/sophgo/Makefile                   |    3 +
 drivers/soc/sophgo/sg2044-topsys.c            |   45 +
 include/dt-bindings/clock/sophgo,sg2044-clk.h |  153 ++
 include/dt-bindings/clock/sophgo,sg2044-pll.h |   27 +
 13 files changed, 2860 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml
 create mode 100644 drivers/clk/sophgo/clk-sg2044-pll.c
 create mode 100644 drivers/clk/sophgo/clk-sg2044.c
 create mode 100644 drivers/soc/sophgo/Kconfig
 create mode 100644 drivers/soc/sophgo/Makefile
 create mode 100644 drivers/soc/sophgo/sg2044-topsys.c
 create mode 100644 include/dt-bindings/clock/sophgo,sg2044-clk.h
 create mode 100644 include/dt-bindings/clock/sophgo,sg2044-pll.h

--
2.49.0