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Message-ID: <SJ1PR11MB6297F9946CEF9C9871FF391B9B842@SJ1PR11MB6297.namprd11.prod.outlook.com>
Date: Fri, 25 Apr 2025 16:56:56 +0000
From: "Salin, Samuel" <samuel.salin@...el.com>
To: "Olech, Milena" <milena.olech@...el.com>,
"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Nguyen, Anthony L"
<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
<przemyslaw.kitszel@...el.com>, "Olech, Milena" <milena.olech@...el.com>,
"Keller, Jacob E" <jacob.e.keller@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH v12 iwl-next 07/11] idpf: add cross
timestamping
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of
> Milena Olech
> Sent: Wednesday, April 16, 2025 5:19 AM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel@...el.com>; Olech, Milena <milena.olech@...el.com>;
> Keller, Jacob E <jacob.e.keller@...el.com>
> Subject: [Intel-wired-lan] [PATCH v12 iwl-next 07/11] idpf: add cross
> timestamping
>
> Add cross timestamp support through virtchnl mailbox messages and directly,
> through PCIe BAR registers. Cross timestamping assumes that both system
> time and device clock time values are cached simultaneously, what is triggered
> by HW. Feature is enabled for both ARM and x86 archs.
>
> Reviewed-by: Jacob Keller <jacob.e.keller@...el.com>
> Signed-off-by: Milena Olech <milena.olech@...el.com>
> ---
> 2.43.5
Tested-by: Samuel Salin <Samuel.salin@...el.com>
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