netdev - Re: [PATCH net-next] net: ethernet: mtk_eth_soc: add support for MT7988 internal 2.5G PHY

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Message-ID: <aBDusgnaJUmZrp_v@makrotopia.org>
Date: Tue, 29 Apr 2025 16:22:26 +0100
From: Daniel Golle <daniel@...rotopia.org>
To: Frank Wunderlich <frank-w@...lic-files.de>
Cc: linux-mediatek@...ts.infradead.org, Felix Fietkau <nbd@....name>,
	John Crispin <john@...ozen.org>,
	Eric Woudstra <ericwouds@...il.com>, Elad Yifee <eladwf@...il.com>,
	Bo-Cun Chen <bc-bocun.chen@...iatek.com>,
	Sky Huang <skylake.huang@...iatek.com>,
	Sean Wang <sean.wang@...iatek.com>,
	Lorenzo Bianconi <lorenzo@...nel.org>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH net-next] net: ethernet: mtk_eth_soc: add support for
 MT7988 internal 2.5G PHY

On Tue, Apr 29, 2025 at 04:12:19PM +0200, Frank Wunderlich wrote:
> Am 26. April 2025 01:08:16 MESZ schrieb Daniel Golle <daniel@...rotopia.org>:
> >On Fri, Apr 25, 2025 at 10:51:18PM +0100, Daniel Golle wrote:
> >> The MediaTek MT7988 SoC comes with an single built-in Ethernet PHY
> >> supporting 2500Base-T/1000Base-T/100Base-TX/10Base-T link partners in
> >> addition to the built-in MT7531-like 1GE switch. The built-in PHY only
> >> supports full duplex.
> >> 
> >> Add muxes allowing to select GMAC2->2.5G PHY path and add basic support
> >> for XGMAC as the built-in 2.5G PHY is internally connected via XGMII.
> >> The XGMAC features will also be used by 5GBase-R, 10GBase-R and USXGMII
> >> SerDes modes which are going to be added once support for standalone PCS
> >> drivers is in place.
> >> 
> >> In order to make use of the built-in 2.5G PHY the appropriate PHY driver
> >> as well as (proprietary) PHY firmware has to be present as well.
> >> 
> >> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> >> ---
> >> [...]
> >> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> >> index 88ef2e9c50fc..e3a8b24dd3d3 100644
> >> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> >> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> >> [...]
> >> @@ -587,6 +603,10 @@
> >>  #define GEPHY_MAC_SEL          BIT(1)
> >>  
> >>  /* Top misc registers */
> >> +#define TOP_MISC_NETSYS_PCS_MUX	0x84
> >
> >This offset still assumes topmisc syscon to start at 0x11d10000.
> >If the pending series[1] adding that syscon at 0x11d10084 gets merged
> >first, this offset will have to be changed to
> >#define TOP_MISC_NETSYS_PCS_MUX	0x0
> >
> >[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20250422132438.15735-8-linux@fw-web.de/
> 
> Imho this should be changed as well
> 
> #define USB_PHY_SWITCH_REG	0x218
> 
> To
> 
> 0x194
> 
> It is used in mtk_eth_path.c set_mux_u3_gmac2_to_qphy

This depends on how we define topmisc for MT7981, as the MTK_U3_COPHY_V2
capability flag is set only for the MT7981 SoC (and hence I would not touch
it in a commit regarding the MT7988 SoC).

In MediaTek's SDK, it is defined as
    topmisc: topmisc@...10000 {
            compatible = "mediatek,mt7981-topmisc", "syscon";
            reg = <0 0x11d10000 0 0x10000>;
            #clock-cells = <1>;
    };