| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250430-kk-tspll-improvements-alignment-v3-7-ab8472e86204@intel.com>
Date: Wed, 30 Apr 2025 15:51:38 -0700
From: Jacob Keller <jacob.e.keller@...el.com>
To: Anthony Nguyen <anthony.l.nguyen@...el.com>,
netdev <netdev@...r.kernel.org>,
Intel Wired LAN <intel-wired-lan@...ts.osuosl.org>
Cc: Jacob Keller <jacob.e.keller@...el.com>,
Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Aleksandr Loktionov <aleksandr.loktionov@...el.com>,
Milena Olech <milena.olech@...el.com>,
Michal Kubiak <michal.kubiak@...el.com>,
Karol Kolacinski <karol.kolacinski@...el.com>
Subject: [PATCH v3 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers
From: Karol Kolacinski <karol.kolacinski@...el.com>
Add ICE_READ_CGU_REG_OR_DIE() and ICE_WRITE_CGU_REG_OR_DIE() helpers to
avoid multiple error checks after calling read/write functions.
Suggested-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
Reviewed-by: Michal Kubiak <michal.kubiak@...el.com>
Reviewed-by: Milena Olech <milena.olech@...el.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 15 +++
drivers/net/ethernet/intel/ice/ice_tspll.c | 160 ++++++----------------------
2 files changed, 47 insertions(+), 128 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index 0ed9b5e2a0afb1d3a0e697a027e3cb125e4db443..fb671e243d5b9520ed3cb1ca3fcb4c697d3a5c94 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -493,5 +493,20 @@ int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);
+#define ICE_READ_CGU_REG_OR_DIE(hw, addr, val) \
+ do { \
+ int __err = ice_read_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);
+#define ICE_WRITE_CGU_REG_OR_DIE(hw, addr, val) \
+ do { \
+ int __err = ice_write_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
+
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index a338cfb1044869f9c844bbd0d6d77987f275f945..acb6a4e77678962f8dea61d914579888c9b87b23 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -132,7 +132,6 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
- int err;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -152,17 +151,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
@@ -171,69 +162,40 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
dw24.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
- err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Configure the TSPLL feedback divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
dw19.ndivratio = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
/* Configure the TSPLL post divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
/* Configure the TSPLL pre divisor and clock source */
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
dw24.ref1588_ck_div = e82x_tspll_params[clk_freq].refclk_pre_div;
dw24.fbdiv_frac = e82x_tspll_params[clk_freq].frac_n_div;
dw24.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
/* Finally, enable the PLL */
dw24.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (!bwm_lf.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
@@ -257,12 +219,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
{
union tspll_cntr_bist_settings cntr_bist;
- int err;
-
- err = ice_read_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
/* Disable sticky lock detection so lock err reported is accurate */
cntr_bist.i_plllock_sel_0 = 0;
cntr_bist.i_plllock_sel_1 = 0;
@@ -294,7 +252,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r23 dw23;
union ice_cgu_r22 dw22;
union ice_cgu_r9 dw9;
- int err;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -313,21 +270,10 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R16, &dw16.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R16, &dw16.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
dw9.time_ref_freq_sel,
@@ -336,10 +282,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
dw23.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
}
/* Set the frequency */
@@ -353,72 +296,42 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
- err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Choose the referenced frequency */
dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
- err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R16, dw16.val);
/* Configure the TSPLL feedback divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
/* Configure the TSPLL post divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
/* These two are constant for E825C */
dw22.time1588clk_div = 5;
dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
/* Configure the TSPLL pre divisor and clock source */
- err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
dw23.ref1588_ck_div = 0;
dw23.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
/* Clear the R24 register. */
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, 0);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0);
/* Finally, enable the PLL */
dw23.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (!ro_lock.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
@@ -442,14 +355,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
union tspll_bw_tdc_e825c bw_tdc;
- int err;
-
- err = ice_read_cgu_reg(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
bw_tdc.i_plllock_sel_1_0 = 0;
-
return ice_write_cgu_reg(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
}
@@ -465,12 +373,8 @@ static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
{
union ice_cgu_r9 r9;
- int err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9.val);
r9.one_pps_out_en = enable;
r9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
return ice_write_cgu_reg(hw, ICE_CGU_R9, r9.val);
--
2.48.1.397.gec9d649cc640
Powered by blists - more mailing lists