netdev - [PATCH v4 15/15] ice: default to TIME

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Message-Id: <20250501-kk-tspll-improvements-alignment-v4-15-24c83d0ce7a8@intel.com>
Date: Thu, 01 May 2025 15:54:26 -0700
From: Jacob Keller <jacob.e.keller@...el.com>
To: Intel Wired LAN <intel-wired-lan@...ts.osuosl.org>, 
 Anthony Nguyen <anthony.l.nguyen@...el.com>, 
 netdev <netdev@...r.kernel.org>
Cc: Jacob Keller <jacob.e.keller@...el.com>, 
 Michal Kubiak <michal.kubiak@...el.com>, 
 Aleksandr Loktionov <aleksandr.loktionov@...el.com>, 
 Karol Kolacinski <karol.kolacinski@...el.com>, 
 Przemek Kitszel <przemyslaw.kitszel@...el.com>, 
 Milena Olech <milena.olech@...el.com>, Paul Menzel <pmenzel@...gen.mpg.de>
Subject: [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on
 E825-C

The driver currently defaults to the internal oscillator as the clock
source for E825-C hardware. While this clock source is labeled TCXO,
indicating a temperature compensated oscillator, this is only true for some
board designs. Many board designs have a less capable oscillator. The
E825-C hardware may also have its clock source set to the TIME_REF pin.
This pin is connected to the DPLL and is often a more stable clock source.
The choice of the internal oscillator is not suitable for all systems,
especially those which want to enable SyncE support.

There is currently no interface available for users to configure the clock
source. Other variants of the E82x board have the clock source configured
in the NVM, but E825-C lacks this capability, so different board designs
cannot select a different default clock via firmware.

In most setups, the TIME_REF is a suitable default clock source.
Additionally, we now fall back to the internal oscillator automatically if
the TIME_REF clock source cannot be locked.

Change the default clock source for E825-C to TIME_REF. Note that the
driver logs a dev_dbg message upon configuring the TSPLL which includes the
clock source and frequency. This can be enabled to confirm which clock
source is in use.

Longterm a proper interface to dynamically introspect and change the clock
source will be designed (perhaps some extension of the DPLL subsystem?)

Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
---
 drivers/net/ethernet/intel/ice/ice_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 7d731d1be862311358943c6922354504ba4721ba..742ffbfba73ca3279cec311ae359ebc6a4e6a584 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2344,7 +2344,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
 		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
 	} else {
 		info->clk_freq = ICE_TSPLL_FREQ_156_250;
-		info->clk_src = ICE_CLK_SRC_TCXO;
+		info->clk_src = ICE_CLK_SRC_TIME_REF;
 	}

 	if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {

-- 
2.48.1.397.gec9d649cc640