netdev - Re: [PATCH] net: phy: add driver for MaxLinear MxL86110 PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <4a6a692f-c6dc-4736-b4b6-b329715d5b96@lunn.ch>
Date: Thu, 15 May 2025 19:54:18 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Stefano Radaelli <stefano.radaelli21@...il.com>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Xu Liang <lxu@...linear.com>
Subject: Re: [PATCH] net: phy: add driver for MaxLinear MxL86110 PHY

> > So does the value 1 here mean 8ns? 0 would be 2ns?
> 
> Setting RXDLY_ENABLE = 1 enables the internal fixed RX_CLK delay
> provided by the PHY, but the actual delay value depends on the
> RX clock frequency: approximately 2 ns at 125 MHz, and ~8 ns at 25 or 2.5 MHz.
> I'm not explicitly selecting 2 or 8 ns, it's applied automatically by the PHY
> based on clock rate.
> 
> Since this delay is additive with the configurable digital RX delay
> set in `CFG1_REG`, I only configure 150 ps in the digital field to
> avoid over-delaying.
> That said, if you prefer, I can disable `RXDLY_ENABLE` and set to 1950 ps
> directly in the digital delay field. Just let me know what you'd prefer here.

Setting only the explicit 1950ps is much easier to understand. Please
do that.

	Andrew