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Message-ID: <20250514195821.56df5c60@kernel.org>
Date: Wed, 14 May 2025 19:58:21 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: Luo Jie <quic_luoj@...cinc.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Paolo Abeni
 <pabeni@...hat.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
 <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Lei Wei
 <quic_leiwei@...cinc.com>, Suruchi Agarwal <quic_suruchia@...cinc.com>,
 Pavithra R <quic_pavir@...cinc.com>, "Simon Horman" <horms@...nel.org>,
 Jonathan Corbet <corbet@....net>, Kees Cook <kees@...nel.org>, "Gustavo A.
 R. Silva" <gustavoars@...nel.org>, "Philipp Zabel"
 <p.zabel@...gutronix.de>, <linux-arm-msm@...r.kernel.org>,
 <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>,
 <linux-hardening@...r.kernel.org>, <quic_kkumarcs@...cinc.com>,
 <quic_linchen@...cinc.com>, <srinivas.kandagatla@...aro.org>,
 <bartosz.golaszewski@...aro.org>, <john@...ozen.org>
Subject: Re: [PATCH net-next v4 00/14] Add PPE driver for Qualcomm IPQ9574
 SoC

On Tue, 13 May 2025 17:58:20 +0800 Luo Jie wrote:
> The PPE (packet process engine) hardware block is available in Qualcomm
> IPQ chipsets that support PPE architecture, such as IPQ9574 and IPQ5332.
> The PPE in the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6
> XGMAC), which are used to connect with external PHY devices by PCS. The
> PPE also includes packet processing offload capabilities for various
> networking functions such as route and bridge flows, VLANs, different
> tunnel protocols and VPN. It also includes an L2 switch function for
> bridging packets among the 6 ethernet ports and the CPU port. The CPU
> port enables packet transfer between the ethernet ports and the ARM
> cores in the SoC, using the ethernet DMA.

Please make sure the code builds cleanly with W=1.
-- 
pw-bot: cr

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