[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <b62d0d20-6ba2-46ff-b581-7fea1e810300@lunn.ch>
Date: Mon, 19 May 2025 14:42:38 +0200
From: Andrew Lunn <andrew@...n.ch>
To: chalianis1@...il.com
Cc: hkallweit1@...il.com, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, linux@...linux.org.uk,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] net: phy: dp83869: fix interrupts issue, not correctly
handled when operate with an optical fiber sfp.
On Sun, May 18, 2025 at 10:24:17PM -0400, chalianis1@...il.com wrote:
> From: Anis Chali <chalianis1@...il.com>
>
> to correctly clear the interrupts both status registers must be read.
>
> from datasheet: http://ti.com/lit/ds/symlink/dp83869hm.pdf
> 7.3.6 Interrupt
> The DP83869HM can be configured to generate an interrupt when changes of internal status occur. The interrupt
> allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be
> selected through the interrupt registers, MICR (12h) and FIBER_INT_EN (C18h). The interrupt status can be
> read from ISR (13h) and FIBER_INT_STTS (C19h) registers. Some interrupts are enabled by default and can
> be disabled through register access. Both the interrupt status registers must be read in order to clear pending
> interrupts. Until the pending interrupts are cleared, new interrupts may not be routed to the interrupt pin.
>
> Signed-off-by: Anis Chali <chalianis1@...il.com>
This seems like something for stable?
https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
Please include a Fixes: tag.
Please base this patch on the net tree:
https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html
> ---
> drivers/net/phy/dp83869.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
> index a62cd838a9ea..98d773175462 100644
> --- a/drivers/net/phy/dp83869.c
> +++ b/drivers/net/phy/dp83869.c
> @@ -25,6 +25,7 @@
> #define DP83869_CFG2 0x14
> #define DP83869_CTRL 0x1f
> #define DP83869_CFG4 0x1e
> +#define DP83869_FX_INT_STS 0xc19
It appears that this is an Extended register, so it belong after
DP83869_FX_CTRL?
Andrew
---
pw-bot: cr
Powered by blists - more mailing lists