netdev - RE: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <IA1PR11MB62419F45C39C48528947652D8B99A@IA1PR11MB6241.namprd11.prod.outlook.com>
Date: Thu, 22 May 2025 14:18:01 +0000
From: "Rinitha, SX" <sx.rinitha@...el.com>
To: "Keller, Jacob E" <jacob.e.keller@...el.com>, Intel Wired LAN
	<intel-wired-lan@...ts.osuosl.org>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, netdev <netdev@...r.kernel.org>
CC: "Keller, Jacob E" <jacob.e.keller@...el.com>, "Kubiak, Michal"
	<michal.kubiak@...el.com>, "Loktionov, Aleksandr"
	<aleksandr.loktionov@...el.com>, "Kolacinski, Karol"
	<karol.kolacinski@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "Olech, Milena" <milena.olech@...el.com>,
	Paul Menzel <pmenzel@...gen.mpg.de>
Subject: RE: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register
 definitions

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@...ts.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@...el.com>; netdev <netdev@...r.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@...el.com>; Kubiak, Michal <michal.kubiak@...el.com>; Loktionov, Aleksandr <aleksandr.loktionov@...el.com>; Kolacinski, Karol <karol.kolacinski@...el.com>; Kitszel, > Przemyslaw <przemyslaw.kitszel@...el.com>; Olech, Milena <milena.olech@...el.com>; Paul Menzel <pmenzel@...gen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions
>
> The E825-C hardware has a slightly different register layout for register
19 of the Clock Generation Unit and TSPLL. The fbdiv_intgr value can be 10 bits wide.
>
> Additionally, most of the fields that were in register 24 are made available in register 23 instead. The programming logic already has a corrected definition for register 23, but it incorrectly still used the 8-bit definition of fbdiv_intgr. This results in truncating some of the values of fbdiv_intgr, including the value used for the 156.25MHz signal.
>
> The driver only used register 24 to obtain the enable status, which we should read from register 23. This results in an incorrect output for the log messages, but does not change any functionality besides disabled-by-default dynamic debug messages.
>
> Fix the register definitions, and adjust the code to properly reflect the enable/disable status in the log messages.
>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.h | 17 ++++++++++++++++-  drivers/net/ethernet/intel/ice/ice_tspll.c  | 17 +++++++----------
> 2 files changed, 23 insertions(+), 11 deletions(-)
>

Tested-by: Rinitha S <sx.rinitha@...el.com> (A Contingent worker at Intel)