netdev - Re: [PATCH v16 22/22] sfc: support pio mapping based on cxl

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Message-ID: <54f84504-b40b-40a1-ac3e-b6baeec8ec0d@gmail.com>
Date: Fri, 23 May 2025 02:13:07 +0100
From: Edward Cree <ecree.xilinx@...il.com>
To: Dan Williams <dan.j.williams@...el.com>, alejandro.lucero-palau@....com,
 linux-cxl@...r.kernel.org, netdev@...r.kernel.org, edward.cree@....com,
 davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com,
 edumazet@...gle.com, dave.jiang@...el.com
Cc: Alejandro Lucero <alucerop@....com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>
Subject: Re: [PATCH v16 22/22] sfc: support pio mapping based on cxl

On 21/05/2025 22:48, Dan Williams wrote:
> Maybe that would be more obvious to me if I knew what a "PIO buffer" was
> used for currently, but some more words about the why of all this would
> help clarify if the design is making the right complexity vs benefit
> tradeoffs.

A PIO buffer is a region of device memory to which the driver can write
 packet data for TX, so that when the device handles the transmit
 doorbell it doesn't have to DMA that data across from host memory.
Essentially it's spending CPU time to save a round-trip across the PCIe
 bus, reducing latency; the driver heuristically decides whether a TX is
 more bandwidth- or latency-sensitive, and in the latter case uses PIO.
I don't know too much about the CXL side of things (hopefully Alejandro
 will elaborate) but AIUI using CXL instead of PCIe for this reduces the
 latency further.

Some of the above information should probably be added to the series
 cover letter or this patch description.