netdev - Re: [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support

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Message-ID: <579b0db7-523c-46fd-897b-58fa0af2a613@lunn.ch>
Date: Sun, 25 May 2025 21:35:09 +0200
From: Andrew Lunn <andrew@...n.ch>
To: george.moussalem@...look.com
Cc: Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Florian Fainelli <f.fainelli@...il.com>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal
 GE PHY support

On Sun, May 25, 2025 at 09:56:04PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@...look.com>
> 
> Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018
> SoC. Its output pins provide an MDI interface to either an external
> switch in a PHY to PHY link scenario or is directly attached to an RJ45
> connector.
> 
> In a phy to phy architecture, DAC values need to be set to accommodate
> for the short cable length. As such, add an optional property to do so.
> 
> In addition, the LDO controller found in the IPQ5018 SoC needs to be
> enabled to driver low voltages to the CMN Ethernet Block (CMN BLK) which
> the GE PHY depends on. The LDO must be enabled in TCSR by writing to a
> specific register. So, adding a property that takes a phandle to the
> TCSR node and the register offset.
> 
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
>  .../devicetree/bindings/net/qca,ar803x.yaml        | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> index 3acd09f0da863137f8a05e435a1fd28a536c2acd..a9e94666ff0af107db4f358b144bf8644c6597e8 100644
> --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> @@ -60,6 +60,29 @@ properties:
>      minimum: 1
>      maximum: 255
>  
> +  qca,dac:
> +    description:
> +      Values for MDAC and EDAC to adjust amplitude, bias current settings,
> +      and error detection and correction algorithm. Only set in a PHY to PHY
> +      link architecture to accommodate for short cable length.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    items:
> +      - items:
> +          - description: value for MDAC. Expected 0x10, if set
> +          - description: value for EDAC. Expected 0x10, if set

DT is not a collection of magic values to be poked into registers.

A bias current should be mA, amplitude probably in mV, and error
detection as an algorithm. 

	Andrew