netdev - Re: [PATCH net-next v4 1/3] dpll: add reference-sync netlink attribute

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Message-ID: <20250529174914.179c1a34@kernel.org>
Date: Thu, 29 May 2025 17:49:14 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
Cc: donald.hunter@...il.com, davem@...emloft.net, edumazet@...gle.com,
 pabeni@...hat.com, horms@...nel.org, vadim.fedorenko@...ux.dev,
 jiri@...nulli.us, anthony.l.nguyen@...el.com, przemyslaw.kitszel@...el.com,
 andrew+netdev@...n.ch, aleksandr.loktionov@...el.com, corbet@....net,
 netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
 intel-wired-lan@...ts.osuosl.org, linux-rdma@...r.kernel.org,
 linux-doc@...r.kernel.org, Milena Olech <milena.olech@...el.com>
Subject: Re: [PATCH net-next v4 1/3] dpll: add reference-sync netlink
 attribute

On Fri, 23 May 2025 19:26:48 +0200 Arkadiusz Kubalewski wrote:
> +The device may support the Reference SYNC feature, which allows the combination
> +of two inputs into a Reference SYNC pair. In this configuration, clock signals
> +from both inputs are used to synchronize the dpll device. The higher frequency
> +signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
> +signal is used to syntonize the output signal of the DPLL device. This feature
> +enables the provision of a high-quality loop bandwidth signal from an external
> +source.

I'm uninitiated into the deeper arts of time sync, but to me this
sounds like a reference clock. Are you trying not to call it clock
because in time clock means a ticker, and this is an oscillator?

> +A capable input provides a list of inputs that can be paired to create a
> +Reference SYNC pair. To control this feature, the user must request a desired
> +state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or
> +``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. Only two pins can be
> +bound to form a Reference SYNC pair at any given time.

Mostly I got confused by the doc saying "Reference SYNC pair".
I was expecting that you'll have to provide 2 ref sync signals.
But IIUC the first signal is still the existing signal we lock
into, so the pair is of a reference sync + an input pin?
Not a pair of two reference syncs.

IOW my reading of the doc made me expect 2 pins to always be passed in
as ref sync, but the example from the cover letter shows only adding
one.