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Message-ID:
<174956707507.2686723.1302808055667500691.stgit@ahduyck-xeon-server.home.arpa>
Date: Tue, 10 Jun 2025 07:51:15 -0700
From: Alexander Duyck <alexander.duyck@...il.com>
To: netdev@...r.kernel.org
Cc: linux@...linux.org.uk, hkallweit1@...il.com, andrew@...n.ch,
davem@...emloft.net, pabeni@...hat.com, kuba@...nel.org
Subject: [net-next PATCH 1/6] net: phy: Add interface types for 50G and 100G
From: Alexander Duyck <alexanderduyck@...com>
Add support for 802.3cd based interface types 50GBASE-R and 100GBASE-P.
This choice in naming is based on section 135 of the 802.3-2022 IEEE
Standard.
In addition it is adding support for what I am referring to as LAUI
which is based on annex 135C of the IEEE Standard, and shares many
similarities with the 25/50G consortium. The main difference between the
two is that IEEE spec refers to LAUI as the AUI before the RS(544/514) FEC,
whereas the 25/50G use this lane and frequency combination after going
through RS(528/514), Base-R or no FEC at all.
Signed-off-by: Alexander Duyck <alexanderduyck@...com>
---
drivers/net/phy/phy-core.c | 3 +++
drivers/net/phy/phy_caps.c | 9 +++++++++
drivers/net/phy/phylink.c | 13 +++++++++++++
drivers/net/phy/sfp-bus.c | 22 ++++++++++++++++++++++
include/linux/phy.h | 12 ++++++++++++
include/linux/sfp.h | 1 +
6 files changed, 60 insertions(+)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index e177037f9110..a8c1b60c46a4 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -142,6 +142,9 @@ int phy_interface_num_ports(phy_interface_t interface)
case PHY_INTERFACE_MODE_RXAUI:
case PHY_INTERFACE_MODE_XAUI:
case PHY_INTERFACE_MODE_1000BASEKX:
+ case PHY_INTERFACE_MODE_50GBASER:
+ case PHY_INTERFACE_MODE_LAUI:
+ case PHY_INTERFACE_MODE_100GBASEP:
return 1;
case PHY_INTERFACE_MODE_QSGMII:
case PHY_INTERFACE_MODE_QUSGMII:
diff --git a/drivers/net/phy/phy_caps.c b/drivers/net/phy/phy_caps.c
index 703321689726..063e4a11614c 100644
--- a/drivers/net/phy/phy_caps.c
+++ b/drivers/net/phy/phy_caps.c
@@ -345,6 +345,15 @@ unsigned long phy_caps_from_interface(phy_interface_t interface)
link_caps |= BIT(LINK_CAPA_40000FD);
break;
+ case PHY_INTERFACE_MODE_50GBASER:
+ case PHY_INTERFACE_MODE_LAUI:
+ link_caps |= BIT(LINK_CAPA_50000FD);
+ break;
+
+ case PHY_INTERFACE_MODE_100GBASEP:
+ link_caps |= BIT(LINK_CAPA_100000FD);
+ break;
+
case PHY_INTERFACE_MODE_INTERNAL:
link_caps |= LINK_CAPA_ALL;
break;
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 0faa3d97e06b..67218d278ce6 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -127,6 +127,9 @@ do { \
#endif
static const phy_interface_t phylink_sfp_interface_preference[] = {
+ PHY_INTERFACE_MODE_100GBASEP,
+ PHY_INTERFACE_MODE_50GBASER,
+ PHY_INTERFACE_MODE_LAUI,
PHY_INTERFACE_MODE_25GBASER,
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_10GBASER,
@@ -274,6 +277,13 @@ static int phylink_interface_max_speed(phy_interface_t interface)
case PHY_INTERFACE_MODE_XLGMII:
return SPEED_40000;
+ case PHY_INTERFACE_MODE_50GBASER:
+ case PHY_INTERFACE_MODE_LAUI:
+ return SPEED_50000;
+
+ case PHY_INTERFACE_MODE_100GBASEP:
+ return SPEED_100000;
+
case PHY_INTERFACE_MODE_INTERNAL:
case PHY_INTERFACE_MODE_NA:
case PHY_INTERFACE_MODE_MAX:
@@ -798,6 +808,9 @@ static int phylink_parse_mode(struct phylink *pl,
case PHY_INTERFACE_MODE_10GKR:
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XLGMII:
+ case PHY_INTERFACE_MODE_50GBASER:
+ case PHY_INTERFACE_MODE_LAUI:
+ case PHY_INTERFACE_MODE_100GBASEP:
caps = ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE);
caps = phylink_get_capabilities(pl->link_config.interface, caps,
RATE_MATCH_NONE);
diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c
index f13c00b5b449..949bf95db8df 100644
--- a/drivers/net/phy/sfp-bus.c
+++ b/drivers/net/phy/sfp-bus.c
@@ -275,6 +275,8 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,
break;
case SFF8024_ECC_100GBASE_CR4:
phylink_set(modes, 100000baseCR4_Full);
+ phylink_set(modes, 50000baseCR2_Full);
+ __set_bit(PHY_INTERFACE_MODE_LAUI, interfaces);
fallthrough;
case SFF8024_ECC_25GBASE_CR_S:
case SFF8024_ECC_25GBASE_CR_N:
@@ -294,6 +296,12 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,
phylink_set(modes, 2500baseT_Full);
__set_bit(PHY_INTERFACE_MODE_2500BASEX, interfaces);
break;
+ case SFF8024_ECC_200GBASE_CR4:
+ phylink_set(modes, 100000baseCR2_Full);
+ __set_bit(PHY_INTERFACE_MODE_100GBASEP, interfaces);
+ phylink_set(modes, 50000baseCR_Full);
+ __set_bit(PHY_INTERFACE_MODE_50GBASER, interfaces);
+ break;
default:
dev_warn(bus->sfp_dev,
"Unknown/unsupported extended compliance code: 0x%02x\n",
@@ -357,6 +365,20 @@ EXPORT_SYMBOL_GPL(sfp_parse_support);
phy_interface_t sfp_select_interface(struct sfp_bus *bus,
const unsigned long *link_modes)
{
+ if (phylink_test(link_modes, 100000baseCR2_Full) ||
+ phylink_test(link_modes, 100000baseKR2_Full) ||
+ phylink_test(link_modes, 100000baseSR2_Full))
+ return PHY_INTERFACE_MODE_100GBASEP;
+
+ if (phylink_test(link_modes, 50000baseCR_Full) ||
+ phylink_test(link_modes, 50000baseKR_Full) ||
+ phylink_test(link_modes, 50000baseSR_Full))
+ return PHY_INTERFACE_MODE_50GBASER;
+
+ if (phylink_test(link_modes, 50000baseCR2_Full) ||
+ phylink_test(link_modes, 50000baseKR2_Full))
+ return PHY_INTERFACE_MODE_LAUI;
+
if (phylink_test(link_modes, 25000baseCR_Full) ||
phylink_test(link_modes, 25000baseKR_Full) ||
phylink_test(link_modes, 25000baseSR_Full))
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e194dad1623d..5095f89b01c6 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -103,6 +103,9 @@ extern const int phy_basic_ports_array[3];
* @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
* @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
* @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
+ * @PHY_INTERFACE_MODE_50GBASER: 50GBase-R - with Clause 134 FEC
+ * @PHY_INTERFACE_MODE_LAUI: 50 Gigabit Attachment Unit Interface
+ * @PHY_INTERFACE_MODE_100GBASEP: 100GBase-P - with Clause 134 FEC
* @PHY_INTERFACE_MODE_MAX: Book keeping
*
* Describes the interface between the MAC and PHY.
@@ -144,6 +147,9 @@ typedef enum {
PHY_INTERFACE_MODE_QUSGMII,
PHY_INTERFACE_MODE_1000BASEKX,
PHY_INTERFACE_MODE_10G_QXGMII,
+ PHY_INTERFACE_MODE_50GBASER,
+ PHY_INTERFACE_MODE_LAUI,
+ PHY_INTERFACE_MODE_100GBASEP,
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
@@ -260,6 +266,12 @@ static inline const char *phy_modes(phy_interface_t interface)
return "qusgmii";
case PHY_INTERFACE_MODE_10G_QXGMII:
return "10g-qxgmii";
+ case PHY_INTERFACE_MODE_50GBASER:
+ return "50gbase-r";
+ case PHY_INTERFACE_MODE_LAUI:
+ return "laui";
+ case PHY_INTERFACE_MODE_100GBASEP:
+ return "100gbase-p";
default:
return "unknown";
}
diff --git a/include/linux/sfp.h b/include/linux/sfp.h
index 60c65cea74f6..c2034a344e49 100644
--- a/include/linux/sfp.h
+++ b/include/linux/sfp.h
@@ -334,6 +334,7 @@ enum {
SFF8024_ECC_10GBASE_T_SR = 0x1c,
SFF8024_ECC_5GBASE_T = 0x1d,
SFF8024_ECC_2_5GBASE_T = 0x1e,
+ SFF8024_ECC_200GBASE_CR4 = 0x40,
};
/* SFP EEPROM registers */
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