netdev - RE: [Intel-wired-lan] [PATCH iwl-next] ice: add recovery clock and clock 1588 control for E825c

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Message-ID: <IA1PR11MB6219AD0507E93B975DC4689B9273A@IA1PR11MB6219.namprd11.prod.outlook.com>
Date: Tue, 17 Jun 2025 11:46:14 +0000
From: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>
To: "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>, "Korba, Przemyslaw"
	<przemyslaw.korba@...el.com>, "intel-wired-lan@...ts.osuosl.org"
	<intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "Olech, Milena" <milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH iwl-next] ice: add recovery clock and
 clock 1588 control for E825c


> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of
> Tony Nguyen
> Sent: Friday, May 9, 2025 10:53 PM
> To: Korba, Przemyslaw <przemyslaw.korba@...el.com>; intel-wired-
> lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Kitszel, Przemyslaw
> <przemyslaw.kitszel@...el.com>; Olech, Milena <milena.olech@...el.com>
> Subject: Re: [Intel-wired-lan] [PATCH iwl-next] ice: add recovery clock and
> clock 1588 control for E825c
> 
> 
> 
> On 5/6/2025 2:35 AM, Przemyslaw Korba wrote:
> > Add control for E825 input pins: phy clock recovery and clock 1588.
> > E825 does not provide control over platform level DPLL but it
> > provides control over PHY clock recovery, and PTP/timestamp driven
> > inputs for platform level DPLL.
> >
> > Introduce a software controlled layer of abstraction to:
> > - create a DPLL of type EEC for E825c,
> > - create recovered clock pin for each PF, and control them through
> > writing to registers,
> > - create pin to control clock 1588 for PF0, and control it through
> > writing to registers.
> >
> > Reviewed-by: Milena Olech <milena.olech@...el.com>
> > Signed-off-by: Przemyslaw Korba <przemyslaw.korba@...el.com>
> > ---
> >   drivers/net/ethernet/intel/ice/ice_dpll.c   | 856 ++++++++++++++++++--
> >   drivers/net/ethernet/intel/ice/ice_dpll.h   |  24 +-
> >   drivers/net/ethernet/intel/ice/ice_main.c   |   3 +-
> >   drivers/net/ethernet/intel/ice/ice_ptp_hw.c |  40 +-
> >   drivers/net/ethernet/intel/ice/ice_ptp_hw.h |   2 +
> >   drivers/net/ethernet/intel/ice/ice_tspll.h  |   7 +
> >   drivers/net/ethernet/intel/ice/ice_type.h   |   6 +
> >   7 files changed, 865 insertions(+), 73 deletions(-)
> >

Apologies for late feedback and not answering directly to original message (I lost it somehow)
This patch requires two more changes:

1) functional, we can't use pf_id for rclk pins initialization in case of E825C devices.
It applies to 2XNC mode variants specifically. There is a mapping needed to achieve
unique pin indexes for PFs from both NAC (there is a function
ice_get_phy_lane_number which covers that and is suitable for other E800 products).

2) after one more analysis of the patch, we think that CLK_OUT pin definition
is redundant (not used) and it would be good to remove it from the patch.

Thanks

Grzegorz