netdev - Re: [net-next PATCH v2 2/2] net: mdio: Add MDIO bus controller for Airoha AN7583

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Message-ID: <065e26cf-1bfb-462c-8cbc-9b4b29f1262d@lunn.ch>
Date: Tue, 17 Jun 2025 15:14:30 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Philipp Zabel <p.zabel@...gutronix.de>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next PATCH v2 2/2] net: mdio: Add MDIO bus controller for
 Airoha AN7583

On Tue, Jun 17, 2025 at 11:16:53AM +0200, Christian Marangi wrote:
> Airoha AN7583 SoC have 2 dedicated MDIO bus controller in the SCU
> register map. To driver register an MDIO controller based on the DT
> reg property and access the register by accessing the parent syscon.
> 
> The MDIO bus logic is similar to the MT7530 internal MDIO bus but
> deviates of some setting and some HW bug.
> 
> On Airoha AN7583 the MDIO clock is set to 25MHz by default and needs to
> be correctly setup to 2.5MHz to correctly work (by setting the divisor
> to 10x).
> 
> There seems to be Hardware bug where AN7583_MII_RWDATA
> is not wiped in the context of unconnected PHY and the
> previous read value is returned.
> 
> Example: (only one PHY on the BUS at 0x1f)
>  - read at 0x1f report at 0x2 0x7500
>  - read at 0x0 report 0x7500 on every address
> 
> To workaround this, we reset the Mdio BUS at every read
> to have consistent values on read operation.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew