netdev - [PATCH v2 09/20] phy: rockchip-samsung-dcphy: switch to FIELD_PREP

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Message-Id: <20250623-byeword-update-v2-9-cf1fc08a2e1f@collabora.com>
Date: Mon, 23 Jun 2025 18:05:37 +0200
From: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
To: Yury Norov <yury.norov@...il.com>, 
 Rasmus Villemoes <linux@...musvillemoes.dk>, 
 Jaehoon Chung <jh80.chung@...sung.com>, 
 Ulf Hansson <ulf.hansson@...aro.org>, Heiko Stuebner <heiko@...ech.de>, 
 Shreeya Patel <shreeya.patel@...labora.com>, 
 Mauro Carvalho Chehab <mchehab@...nel.org>, 
 Sandy Huang <hjc@...k-chips.com>, Andy Yan <andy.yan@...k-chips.com>, 
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, 
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, 
 Nicolas Frattaroli <frattaroli.nicolas@...il.com>, 
 Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, 
 Jaroslav Kysela <perex@...ex.cz>, Takashi Iwai <tiwai@...e.com>, 
 Andrew Lunn <andrew+netdev@...n.ch>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Shawn Lin <shawn.lin@...k-chips.com>, 
 Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof Wilczyński <kwilczynski@...nel.org>, 
 Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>, 
 Bjorn Helgaas <bhelgaas@...gle.com>, Chanwoo Choi <cw00.choi@...sung.com>, 
 MyungJoo Ham <myungjoo.ham@...sung.com>, 
 Kyungmin Park <kyungmin.park@...sung.com>, Qin Jian <qinjian@...lus1.com>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, Nathan Chancellor <nathan@...nel.org>, 
 Nick Desaulniers <nick.desaulniers+lkml@...il.com>, 
 Bill Wendling <morbo@...gle.com>, Justin Stitt <justinstitt@...gle.com>
Cc: kernel@...labora.com, linux-kernel@...r.kernel.org, 
 linux-mmc@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
 linux-rockchip@...ts.infradead.org, linux-media@...r.kernel.org, 
 dri-devel@...ts.freedesktop.org, linux-phy@...ts.infradead.org, 
 linux-sound@...r.kernel.org, netdev@...r.kernel.org, 
 linux-stm32@...md-mailman.stormreply.com, linux-pci@...r.kernel.org, 
 linux-pm@...r.kernel.org, linux-clk@...r.kernel.org, llvm@...ts.linux.dev, 
 Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Subject: [PATCH v2 09/20] phy: rockchip-samsung-dcphy: switch to
 FIELD_PREP_WM16 macro

The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

phy-rockchip-samsung-dcphy is actually an exemplary example, where the
similarities to FIELD_PREP were spotted and the driver local macro has
the same semantics as the new FIELD_PREP_WM16 hw_bitfield.h macro.

Still, get rid of FIELD_PREP_HIWORD now that a shared implementation
exists, replacing the two instances of it with FIELD_PREP_WM16. This
gives us slightly better error checking; the value is now checked to fit
in 16 bits.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
---
 drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
index 28a052e17366516d5a99988bec9a52e3f0f09101..4508a314727232473e90fd1649ec0f2829b65c49 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
@@ -8,6 +8,7 @@
 #include <dt-bindings/phy/phy.h>
 #include <linux/bitfield.h>
 #include <linux/clk.h>
+#include <linux/hw_bitfield.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/mfd/syscon.h>
@@ -20,12 +21,6 @@
 #include <linux/regmap.h>
 #include <linux/reset.h>

-#define FIELD_PREP_HIWORD(_mask, _val)		\
-	(					\
-		FIELD_PREP((_mask), (_val)) |	\
-		((_mask) << 16)			\
-	)
-
 #define BIAS_CON0		0x0000
 #define I_RES_CNTL_MASK		GENMASK(6, 4)
 #define I_RES_CNTL(x)		FIELD_PREP(I_RES_CNTL_MASK, x)
@@ -252,8 +247,8 @@

 /* MIPI_CDPHY_GRF registers */
 #define MIPI_DCPHY_GRF_CON0		0x0000
-#define S_CPHY_MODE			FIELD_PREP_HIWORD(BIT(3), 1)
-#define M_CPHY_MODE			FIELD_PREP_HIWORD(BIT(0), 1)
+#define S_CPHY_MODE			FIELD_PREP_WM16(BIT(3), 1)
+#define M_CPHY_MODE			FIELD_PREP_WM16(BIT(0), 1)

 enum hs_drv_res_ohm {
 	STRENGTH_30_OHM = 0x8,

-- 
2.50.0