netdev - Re: [PATCH net-next 2/2] ARM: dts: Fix up wrv54g device tree

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Message-ID: <CACRpkdbr8-0=bZ0mRkZ9DnWrKZbQM3AuNdzbxyWTX1qiEAgJjw@mail.gmail.com>
Date: Tue, 24 Jun 2025 11:07:16 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Andrew Lunn <andrew@...n.ch>
Cc: Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Imre Kaloz <kaloz@...nwrt.org>, Frederic Lambert <frdrc66@...il.com>, Gabor Juhos <juhosg@...nwrt.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, netdev@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next 2/2] ARM: dts: Fix up wrv54g device tree

On Tue, Jun 24, 2025 at 10:16 AM Andrew Lunn <andrew@...n.ch> wrote:
> On Tue, Jun 24, 2025 at 09:41:12AM +0200, Linus Walleij wrote:

> > +                             ethernet-port@0 {
> > +                                     reg = <0>;
> > +                                     label = "1";
> > +                                     phy-mode = "rgmii";
>
> If this is an internal PHY, it would be better to use 'internal'. I
> would like to avoid all the issues around 'rgmii' vs 'rgmii-id'.

OK you're right, I'll rewrite this and the example in the binding
to use "internal", as this is what it is.

The fifth PHY is inside the switch, yet "external" in a way.
They are all managed by external MDIO though, see below.

> > +                             ethernet-port@4 {
> > +                                     reg = <4>;
> > +                                     ethernet = <&ethb>;
> > +                                     phy-mode = "rgmii-id";
> > +                                     fixed-link {
> > +                                             speed = <100>;
> > +                                             full-duplex;
> > +                                     };
>
> That is a bit odd, rgmii-id, yet speed limited to 100. It would be
> good to add a comment about this.

Copy/paste error when working with old code :(

It's good old "mii"

> This is all confusing. Do you have the board, or a schematic for it?

I was confused because I managed to find phonto of thePCB
for the board in question:
https://real.phj.hu/wrv54g/

If you look on the bottom of the image, there is a component
to the LAN ports, chip tag reads: "SWAP net NS604009" (made 0421)
but I think it's just one of these isolation transformers so the
PHYs are indeed internal (the KS8995 is the component above
with the heat sink mounted on top).

> >                       mdio {
> >                               #address-cells = <1>;
> >                               #size-cells = <0>;
> >
> > -                             /* Should be ports 1-4 on the KS8995 switch */
> > +                             /* Should be LAN ports 1-4 on the KS8995 switch */
> > +                             phy1: ethernet-phy@1 {
> > +                                     reg = <1>;
> > +                             };
> > +                             phy2: ethernet-phy@2 {
> > +                                     reg = <2>;
> > +                             };
> > +                             phy3: ethernet-phy@3 {
> > +                                     reg = <3>;
> > +                             };
> >                               phy4: ethernet-phy@4 {
> >                                       reg = <4>;
> >                               };
>
> This node is the SoC interface MDIO bus. Why would the internal PHYs
> of switch bus on the SoC MDIO bus? I would expect the switch to have
> its own MDIO bus and place its PHYs there.

This switch is so old that in difference from other DSA switches it does
not have its own internal MDIO bus... I know for sure because I'm working
on another device and I can access all PHY:s over MDIO. It depends
on an external MDIO connection.

Here is a datasheet:
https://docs.rs-online.com/0889/0900766b81385414.pdf

On page 45 it says:
"A standard MIIM interface is provided for all five PHY devices in the
 KS8995MA/FQ. An external device with MDC/MDIO capability is able
 to read PHY status or to configure PHY settings."

I'll update and repost so it makes more sense!

Yours,
Linus Walleij