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Message-Id: <20250623-kk-tspll-improvements-alignment-v1-1-fe9a50620700@intel.com>
Date: Mon, 23 Jun 2025 17:29:57 -0700
From: Jacob Keller <jacob.e.keller@...el.com>
To: Intel Wired LAN <intel-wired-lan@...ts.osuosl.org>
Cc: Jacob Keller <jacob.e.keller@...el.com>,
Anthony Nguyen <anthony.l.nguyen@...el.com>, netdev@...r.kernel.org,
Karol Kolacinski <karol.kolacinski@...el.com>
Subject: [PATCH 1/8] ice: clear time_sync_en field for E825-C during
reprogramming
When programming the Clock Generation Unit for E285-C hardware, we need
to clear the time_sync_en bit of the DWORD 9 before we set the
frequency.
Co-developed-by: Karol Kolacinski <karol.kolacinski@...el.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 08af4ced50eb877dce5944d87a90d0dcdb49ff2e..5a2ddd3feba2f96d14c817a697423219cadc45e6 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -342,6 +342,14 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return err;
}
+ if (dw9.time_sync_en) {
+ dw9.time_sync_en = 0;
+
+ err = ice_write_cgue_reg(hw, ICE_CGU_R9, dw9.val);
+ if (err)
+ return err;
+ }
+
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
@@ -353,6 +361,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
+ dw9.time_sync_en = 1;
err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
if (err)
return err;
--
2.48.1.397.gec9d649cc640
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