netdev - Re: [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers

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Message-ID: <7dfba01a-6ede-44c2-87e3-3ecb439b48e3@kernel.org>
Date: Tue, 24 Jun 2025 18:02:39 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Laura Nao <laura.nao@...labora.com>, mturquette@...libre.com,
 sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com,
 p.zabel@...gutronix.de, richardcochran@...il.com
Cc: guangjie.song@...iatek.com, wenst@...omium.org,
 linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
 kernel@...labora.com
Subject: Re: [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196
 peripheral clock controllers

On 24/06/2025 16:32, Laura Nao wrote:
> +  '#reset-cells':
> +    const: 1
> +    description:
> +      Reset lines for PEXTP0/1 and UFS blocks.
> +
> +  mediatek,hardware-voter:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
> +      MCU manages clock and power domain control across the AP and other
> +      remote processors. By aggregating their votes, it ensures clocks are
> +      safely enabled/disabled and power domains are active before register
> +      access.

Resource voting is not via any phandle, but either interconnects or
required opps for power domain.

I already commented on this, so don't send v3 with the same.

Best regards,
Krzysztof