lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <IA1PR11MB62195A68F29383B92CDC150A9278A@IA1PR11MB6219.namprd11.prod.outlook.com>
Date: Tue, 24 Jun 2025 19:44:48 +0000
From: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>
To: "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "Olech, Milena" <milena.olech@...el.com>,
	"Korba, Przemyslaw" <przemyslaw.korba@...el.com>
Subject: RE: [PATCH v2 iwl-net] ice: add recovery clock and clock 1588 control
 for E825c

> -----Original Message-----
> From: Nitka, Grzegorz <grzegorz.nitka@...el.com>
> Sent: Tuesday, June 24, 2025 9:22 PM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel@...el.com>; Olech, Milena <milena.olech@...el.com>;
> Korba, Przemyslaw <przemyslaw.korba@...el.com>; Nitka, Grzegorz
> <grzegorz.nitka@...el.com>
> Subject: [PATCH v2 iwl-net] ice: add recovery clock and clock 1588 control for
> E825c
> 
> From: Przemyslaw Korba <przemyslaw.korba@...el.com>
> 
> Add control for E825 input pins: phy clock recovery and clock 1588.
> E825 does not provide control over platform level DPLL but it
> provides control over PHY clock recovery, and PTP/timestamp driven
> inputs for platform level DPLL.
> 
> Introduce a software controlled layer of abstraction to:
> - create a DPLL of type EEC for E825c,
> - create recovered clock pin for each PF, and control them through
> writing to registers,
> - create pin to control clock 1588 for PF0, and control it through
> writing to registers.
> 
> Reviewed-by: Milena Olech <milena.olech@...el.com>
> Co-developed-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Przemyslaw Korba <przemyslaw.korba@...el.com>

I put wrong list in the title. It should go to 'net-next', not 'net'.
Will fix it in another patch.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ