netdev - Re: [PATCH] net: stmmac: Fix interrupt handling for level-triggered mode in DWC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20250625153933.7757fde3@kernel.org>
Date: Wed, 25 Jun 2025 15:39:33 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: EricChan <chenchuangyu@...omi.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, <davem@...emloft.net>, Eric Dumazet
 <edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>, Maxime Coquelin
 <mcoquelin.stm32@...il.com>, "Alexandre Torgue"
 <alexandre.torgue@...s.st.com>, Feiyang Chen <chenfeiyang@...ngson.cn>,
 Serge Semin <fancer.lancer@...il.com>, Yinggang Gu
 <guyinggang@...ngson.cn>, Huacai Chen <chenhuacai@...nel.org>, Yanteng Si
 <si.yanteng@...ux.dev>, <netdev@...r.kernel.org>,
 <linux-stm32@...md-mailman.stormreply.com>,
 <linux-arm-kernel@...ts.infradead.org>, xiaojianfeng
 <xiaojianfeng1@...omi.com>, xiongliang <xiongliang@...omi.com>
Subject: Re: [PATCH] net: stmmac: Fix interrupt handling for level-triggered
 mode in DWC_XGMAC2

On Wed, 25 Jun 2025 10:51:34 +0800 EricChan wrote:
> According to the Synopsys Controller IP XGMAC-10G Ethernet MAC Databook
> v3.30a (section 2.7.2), when the INTM bit in the DMA_Mode register is set
> to 2, the sbd_perch_tx_intr_o[] and sbd_perch_rx_intr_o[] signals operate
> in level-triggered mode. However, in this configuration, the DMA does not
> assert the XGMAC_NIS status bit for Rx or Tx interrupt events.
> 
> This creates a functional regression where the condition
> if (likely(intr_status & XGMAC_NIS)) in dwxgmac2_dma_interrupt() will
> never evaluate to true, preventing proper interrupt handling for
> level-triggered mode. The hardware specification explicitly states that
> "The DMA does not assert the NIS status bit for the Rx or Tx interrupt
> events" (Synopsys DWC_XGMAC2 Databook v3.30a, sec. 2.7.2).
> 
> The fix ensures correct handling of both edge and level-triggered
> interrupts while maintaining backward compatibility with existing
> configurations.

Could you please add a Fixes tag pointing to the commit in which 
the problem was introduced?

If the device you're working with is publicly available it may
also be worth mentioning what it is in the commit message.
Or at least mentioning whether you tested this on real HW,
or in simulation, or not at all.
-- 
pw-bot: cr