netdev - Re: [PATCH net-next v2 05/18] net: macb: use BIT() macro for capability definitions

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Message-ID: <fd88c994-c4f0-4ba1-bc8a-908cfb3b5498@linux.dev>
Date: Tue, 1 Jul 2025 11:35:10 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Théo Lebrun <theo.lebrun@...tlin.com>,
 Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Nicolas Ferre <nicolas.ferre@...rochip.com>,
 Claudiu Beznea <claudiu.beznea@...on.dev>,
 Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Alexandre Ghiti <alex@...ti.fr>, Samuel Holland <samuel.holland@...ive.com>,
 Richard Cochran <richardcochran@...il.com>,
 Russell King <linux@...linux.org.uk>,
 Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
 Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
 Gregory CLEMENT <gregory.clement@...tlin.com>,
 Cyrille Pitchen <cyrille.pitchen@...el.com>,
 Harini Katakam <harini.katakam@...inx.com>,
 Rafal Ozieblo <rafalo@...ence.com>,
 Haavard Skinnemoen <hskinnemoen@...el.com>, Jeff Garzik <jeff@...zik.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
 linux-mips@...r.kernel.org, Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
 Tawfik Bayouk <tawfik.bayouk@...ileye.com>, Andrew Lunn <andrew@...n.ch>
Subject: Re: [PATCH net-next v2 05/18] net: macb: use BIT() macro for
 capability definitions

On 6/27/25 05:08, Théo Lebrun wrote:
> Replace all capabilities values by calls to the BIT() macro.
> 
> Reviewed-by: Andrew Lunn <andrew@...n.ch>
> Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com>
> ---
>  drivers/net/ethernet/cadence/macb.h | 40 ++++++++++++++++++-------------------
>  1 file changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index c9a5c8beb2fa8166195d1d83f187d2d0c62668a8..3b43cb9468e3618754ff2bc6c5f360447bdeeed0 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -727,26 +727,26 @@
>  #define MACB_MAN_C45_CODE			2
>  
>  /* Capability mask bits */
> -#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x00000001
> -#define MACB_CAPS_USRIO_HAS_CLKEN		0x00000002
> -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII	0x00000004
> -#define MACB_CAPS_NO_GIGABIT_HALF		0x00000008
> -#define MACB_CAPS_USRIO_DISABLED		0x00000010
> -#define MACB_CAPS_JUMBO				0x00000020
> -#define MACB_CAPS_GEM_HAS_PTP			0x00000040
> -#define MACB_CAPS_BD_RD_PREFETCH		0x00000080
> -#define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
> -#define MACB_CAPS_MIIONRGMII			0x00000200
> -#define MACB_CAPS_NEED_TSUCLK			0x00000400
> -#define MACB_CAPS_QUEUE_DISABLE			0x00000800
> -#define MACB_CAPS_PCS				0x01000000
> -#define MACB_CAPS_HIGH_SPEED			0x02000000
> -#define MACB_CAPS_CLK_HW_CHG			0x04000000
> -#define MACB_CAPS_MACB_IS_EMAC			0x08000000
> -#define MACB_CAPS_FIFO_MODE			0x10000000
> -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
> -#define MACB_CAPS_SG_DISABLED			0x40000000
> -#define MACB_CAPS_MACB_IS_GEM			0x80000000
> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE		BIT(0)
> +#define MACB_CAPS_USRIO_HAS_CLKEN		BIT(1)
> +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII	BIT(2)
> +#define MACB_CAPS_NO_GIGABIT_HALF		BIT(3)
> +#define MACB_CAPS_USRIO_DISABLED		BIT(4)
> +#define MACB_CAPS_JUMBO				BIT(5)
> +#define MACB_CAPS_GEM_HAS_PTP			BIT(6)
> +#define MACB_CAPS_BD_RD_PREFETCH		BIT(7)
> +#define MACB_CAPS_NEEDS_RSTONUBR		BIT(8)
> +#define MACB_CAPS_MIIONRGMII			BIT(9)
> +#define MACB_CAPS_NEED_TSUCLK			BIT(10)
> +#define MACB_CAPS_QUEUE_DISABLE			BIT(11)
> +#define MACB_CAPS_PCS				BIT(24)
> +#define MACB_CAPS_HIGH_SPEED			BIT(25)
> +#define MACB_CAPS_CLK_HW_CHG			BIT(26)
> +#define MACB_CAPS_MACB_IS_EMAC			BIT(27)
> +#define MACB_CAPS_FIFO_MODE			BIT(28)
> +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE	BIT(29)
> +#define MACB_CAPS_SG_DISABLED			BIT(30)
> +#define MACB_CAPS_MACB_IS_GEM			BIT(31)
>  
>  /* LSO settings */
>  #define MACB_LSO_UFO_ENABLE			0x01
> 

Reviewed-by: Sean Anderson <sean.anderson@...ux.dev>

But since these capabilities don't correspond to hardware registers, can
you add a follow-up patch to remove the gap between QUEUE_DISABLE and
PCS?