netdev - Re: [PATCH v4 2/4] pinctrl: renesas: rzg2l: Pass OEN pin names

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Message-ID: <CAMuHMdVsvWrTBXkZ4etWy-8sPH4TG7AEyD_Z27RBWutNvpmUHA@mail.gmail.com>
Date: Wed, 2 Jul 2025 11:47:27 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: John Madieu <john.madieu.xa@...renesas.com>, prabhakar.mahadev-lad.rj@...renesas.com
Cc: magnus.damm@...il.com, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org, 
	richardcochran@...il.com, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-clk@...r.kernel.org, netdev@...r.kernel.org, biju.das.jz@...renesas.com, 
	john.madieu@...il.com
Subject: Re: [PATCH v4 2/4] pinctrl: renesas: rzg2l: Pass OEN pin names

Hi John, Prabhakar,

On Wed, 2 Jul 2025 at 02:57, John Madieu <john.madieu.xa@...renesas.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Pass the OEN pin names via the SoC-specific hardware configuration
> structure to allow reuse of rzv2h_oen_read() and rzv2h_oen_write()
> on multiple SoCs.
>
> On the RZ/V2H(P) and RZ/G3E SoCs, the PFC_OEN register is located at the
> same offset. However, the register controls different pins on each SoC.
> Hardcoding the pin names in the common logic prevents reusability.
>
> Extend struct rzg2l_hwcfg to include an array of OEN pin names and its
> length. Use these values in rzv2h_pin_to_oen_bit() to determine the bit
> position dynamically based on the active SoC.
>
> This enables shared handling of OEN register access while accounting for
> SoC-specific pin mappings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -257,6 +257,8 @@ enum rzg2l_iolh_index {
>   * @func_base: base number for port function (see register PFC)
>   * @oen_max_pin: the maximum pin number supporting output enable
>   * @oen_max_port: the maximum port number supporting output enable
> + * @oen_pin_names: array of pin names for output enable
> + * @oen_pin_names_len: length of the oen_pin_names array
>   */
>  struct rzg2l_hwcfg {
>         const struct rzg2l_register_offsets regs;
> @@ -269,6 +271,8 @@ struct rzg2l_hwcfg {
>         u8 func_base;
>         u8 oen_max_pin;
>         u8 oen_max_port;
> +       const char * const *oen_pin_names;
> +       u8 oen_pin_names_len;

Please exchange the order of the members, so the u8 fits in the
existing hole.

However, I think you better drop this patch, and use the existing
rzg2l_pinctrl_data.oen_{read,write]() abstraction instead.

>  };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds