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Message-ID: <175199138810.517400.11158407408233098308.robh@kernel.org>
Date: Tue, 8 Jul 2025 11:16:28 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Chen-Yu Tsai <wens@...nel.org>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, Conor Dooley <conor+dt@...nel.org>,
Samuel Holland <samuel@...lland.org>,
linux-arm-kernel@...ts.infradead.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, Jakub Kicinski <kuba@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, linux-kernel@...r.kernel.org,
Jernej Skrabec <jernej@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Eric Dumazet <edumazet@...gle.com>,
Andre Przywara <andre.przywara@....com>,
"David S. Miller" <davem@...emloft.net>,
linux-sunxi@...ts.linux.dev
Subject: Re: [PATCH RFT net-next 01/10] dt-bindings: net: sun8i-emac: Add
A523 GMAC200 compatible
On Wed, 02 Jul 2025 00:57:47 +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@...e.org>
>
> The Allwinner A523 SoC family has a second Ethernet controller, called
> the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
> numbering. This controller, according to BSP sources, is fully
> compatible with a slightly newer version of the Synopsys DWMAC core.
> The glue layer around the controller is the same as found around older
> DWMAC cores on Allwinner SoCs. The only slight difference is that since
> this is the second controller on the SoC, the register for the clock
> delay controls is at a different offset. Last, the integration includes
> a dedicated clock gate for the memory bus and the whole thing is put in
> a separately controllable power domain.
>
> Add a compatible string entry for it, and work in the requirements for
> a second clock and a power domain.
>
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>
> ---
> .../net/allwinner,sun8i-a83t-emac.yaml | 68 ++++++++++++++++++-
> 1 file changed, 66 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
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