netdev - Re: [PATCH mlx5-next 3/8] net/mlx5: Add support for device steering tag

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20250708055133.GD592765@unreal>
Date: Tue, 8 Jul 2025 08:51:33 +0300
From: Leon Romanovsky <leon@...nel.org>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: Yishai Hadas <yishaih@...dia.com>, Andrew Lunn <andrew+netdev@...n.ch>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, linux-rdma@...r.kernel.org,
	netdev@...r.kernel.org, Paolo Abeni <pabeni@...hat.com>,
	Saeed Mahameed <saeedm@...dia.com>,
	Tariq Toukan <tariqt@...dia.com>
Subject: Re: [PATCH mlx5-next 3/8] net/mlx5: Add support for device steering
 tag

On Mon, Jul 07, 2025 at 08:03:03PM +0300, Leon Romanovsky wrote:
> From: Yishai Hadas <yishaih@...dia.com>
> 
> Background, from PCIe specification 6.2.
> 
> TLP Processing Hints (TPH)
> --------------------------
> TLP Processing Hints is an optional feature that provides hints in
> Request TLP headers to facilitate optimized processing of Requests that
> target Memory Space. These Processing Hints enable the system hardware
> (e.g., the Root Complex and/or Endpoints) to optimize platform
> resources such as system and memory interconnect on a per TLP basis.
> Steering Tags are system-specific values used to identify a processing
> resource that a Requester explicitly targets. System software discovers
> and identifies TPH capabilities to determine the Steering Tag allocation
> for each Function that supports TPH.
> 
> This patch adds steering tag support for mlx5 based NICs by:
> 
> - Enabling the TPH functionality over PCI if both FW and OS support it.
> - Managing steering tags and their matching steering indexes by
>   writing a ST to an ST index over the PCI configuration space.
> - Exposing APIs to upper layers (e.g.,mlx5_ib) to allow usage of
>   the PCI TPH infrastructure.
> 
> Further details:
> - Upon probing of a device, the feature will be enabled based
>   on both capability detection and OS support.
> 
> - It will retrieve the appropriate ST for a given CPU ID and memory
>   type using the pcie_tph_get_cpu_st() API.
> 
> - It will track available ST indices according to the configuration
>   space table size (expected to be 63 entries), reserving index 0 to
>   indicate non-TPH use.
> 
> - It will assign a free ST index with a ST using the
>   pcie_tph_set_st_entry() API.
> 
> - It will reuse the same index for identical (CPU ID + memory type)
>   combinations by maintaining a reference count per entry.
> 
> - It will expose APIs to upper layers (e.g., mlx5_ib) to allow usage of
>   the PCI TPH infrastructure.
> 
> - SF will use its parent PF stuff.
> 
> Signed-off-by: Yishai Hadas <yishaih@...dia.com>
> Signed-off-by: Leon Romanovsky <leonro@...dia.com>
> ---
>  .../net/ethernet/mellanox/mlx5/core/Makefile  |   5 +
>  .../net/ethernet/mellanox/mlx5/core/lib/st.c  | 162 ++++++++++++++++++
>  .../net/ethernet/mellanox/mlx5/core/main.c    |   2 +
>  .../ethernet/mellanox/mlx5/core/mlx5_core.h   |   9 +
>  include/linux/mlx5/driver.h                   |  20 +++
>  5 files changed, 198 insertions(+)
>  create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/lib/st.c

<...>

> +	if (mlx5_core_is_sf(dev))

Somehow this line was lost during rebase.
This should be if (IS_ENABLED(CONFIG_MLX5_SF) && mlx5_core_is_sf(dev)) 

Thanks