| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250710-qcom_ipq5424_nsscc-v3-0-f149dc461212@quicinc.com>
Date: Thu, 10 Jul 2025 20:28:08 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Anusha Rao
<quic_anusha@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
"Philipp
Zabel" <p.zabel@...gutronix.de>,
Richard Cochran <richardcochran@...il.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <netdev@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
<quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
<quic_pavir@...cinc.com>, <quic_suruchia@...cinc.com>,
Luo Jie
<quic_luoj@...cinc.com>,
Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>,
Konrad Dybcio
<konrad.dybcio@....qualcomm.com>
Subject: [PATCH v3 00/10] Add Network Subsystem (NSS) clock controller
support for IPQ5424 SoC
The NSS clock controller on the IPQ5424 SoC provides clocks and resets
to the networking related hardware blocks such as the Packet Processing
Engine (PPE) and UNIPHY (PCS). Its parent clocks are sourced from the
GCC, CMN PLL, and UNIPHY blocks.
Additionally, register the gpll0_out_aux GCC clock, which serves as one
of the parent clocks for some of the NSS clocks.
The NSS NoC clocks are also enabled to use the icc-clk framework, enabling
the creation of interconnect paths for the network subsystem’s connections
with these NoCs.
The NSS clock controller receives its input clocks from the CMN PLL outputs.
The related patch series which adds support for IPQ5424 SoC in the CMN PLL
driver is listed below.
https://lore.kernel.org/all/20250610-qcom_ipq5424_cmnpll-v3-0-ceada8165645@quicinc.com/
To: Georgi Djakov <djakov@...nel.org>
To: Rob Herring <robh@...nel.org>
To: Krzysztof Kozlowski <krzk+dt@...nel.org>
To: Conor Dooley <conor+dt@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>
To: Michael Turquette <mturquette@...libre.com>
To: Stephen Boyd <sboyd@...nel.org>
To: Anusha Rao <quic_anusha@...cinc.com>
To: Konrad Dybcio <konradybcio@...nel.org>
To: Philipp Zabel <p.zabel@...gutronix.de>
To: Richard Cochran <richardcochran@...il.com>
To: Catalin Marinas <catalin.marinas@....com>
To: Will Deacon <will@...nel.org>
Cc: linux-arm-msm@...r.kernel.org
Cc: linux-pm@...r.kernel.org
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: linux-clk@...r.kernel.org
Cc: netdev@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: quic_kkumarcs@...cinc.com
Cc: quic_linchen@...cinc.com
Cc: quic_leiwei@...cinc.com
Cc: quic_pavir@...cinc.com
Cc: quic_suruchia@...cinc.com
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
Changes in v3:
- Remove frequency suffix from clock names for PPE and NSS clocks in
IPQ9574 DT binding and DTS.
- Update IPQ5424 DT bindings and DTS to as per new PPE and NSS clock names.
- Expand the register region of IPQ5424 NSSCC to utilize the entire 0x100_000
address range, ensuring inclusion of the wrapper region.
- Collect the reviewed-by tags.
- Link to v2: https://lore.kernel.org/r/20250627-qcom_ipq5424_nsscc-v2-0-8d392f65102a@quicinc.com
Changes in v2:
- Add new, separate clock names "nss" and "ppe" in dtbindings to support
the IPQ5424 SoC.
- Wrap the commit message body at 75 columns.
- Fix the indentation issue in the `IPQ_NSSCC_5424` Kconfig entry.
- Enhance the commit message for the defconfig patch to clarify the requirement
for enabling `IPQ_NSSCC_5424`.
- Link to v1: https://lore.kernel.org/r/20250617-qcom_ipq5424_nsscc-v1-0-4dc2d6b3cdfc@quicinc.com
---
Luo Jie (10):
dt-bindings: interconnect: Add Qualcomm IPQ5424 NSSNOC IDs
clk: qcom: ipq5424: Enable NSS NoC clocks to use icc-clk
dt-bindings: clock: gcc-ipq5424: Add definition for GPLL0_OUT_AUX
clock: qcom: gcc-ipq5424: Add gpll0_out_aux clock
dt-bindings: clock: ipq9574: Rename NSS CC source clocks to drop rate
arm64: dts: qcom: ipq9574: Rename NSSCC source clock names to drop rate
dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC
clk: qcom: Add NSS clock controller driver for IPQ5424
arm64: dts: qcom: ipq5424: Add NSS clock controller node
arm64: defconfig: Build NSS clock controller driver for IPQ5424
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 26 +-
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 +-
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5424.c | 21 +-
drivers/clk/qcom/nsscc-ipq5424.c | 1340 ++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq5424-gcc.h | 3 +-
include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 +
include/dt-bindings/interconnect/qcom,ipq5424.h | 19 +
include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +
12 files changed, 1553 insertions(+), 14 deletions(-)
---
base-commit: b27cc623e01be9de1580eaa913508b237a7a9673
change-id: 20250709-qcom_ipq5424_nsscc-389d30977b1b
prerequisite-change-id: 20250610-qcom_ipq5424_cmnpll-22b232bb18fd:v3
prerequisite-patch-id: dc3949e10baf58f8c28d24bb3ffd347a78a1a2ee
prerequisite-patch-id: da645619780de3186a3cccf25beedd4fefab36df
prerequisite-patch-id: c7fbe69bfd80fc41c3f76104e36535ee547583db
prerequisite-patch-id: 541f835fb279f83e6eb2405c531bd7da9aacf4bd
Best regards,
--
Luo Jie <quic_luoj@...cinc.com>
Powered by blists - more mailing lists