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Message-ID: <2154c04a-b9ad-4382-95c9-1e3d7d342c9b@lunn.ch>
Date: Tue, 15 Jul 2025 17:10:51 +0200
From: Andrew Lunn <andrew@...n.ch>
To: "G Thomas, Rohan" <rohan.g.thomas@...era.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Serge Semin <fancer.lancer@...il.com>,
Romain Gantois <romain.gantois@...tlin.com>, netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Matthew Gerlach <matthew.gerlach@...era.com>
Subject: Re: [PATCH net-next 2/3] net: stmmac: xgmac: Correct supported speed
modes
> As per the XGMAC databook ver 3.10a, GMIISEL bit of MAC_HW_Feature_0
> register indicates whether the XGMAC IP on the SOC is synthesized with
> DWCXG_GMII_SUPPORT. Specifically, it states:
> "1000/100/10 Mbps Support. This bit is set to 1 when the GMII Interface
> option is selected."
>
> So yes, it’s likely that Serge was working with a SERDES interface which
> doesn't support 10/100Mbps speeds. Do you think it would be appropriate
> to add a check for this bit before enabling 10/100Mbps speeds?
Yes.
That is the problem with stuff you can synthesizer. You have no idea
what it actually is unless you read all the self enumerating
registers. Flexibility at the cost of complexity.
Andrew
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