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Message-ID: <aHgGJ6sia5Xe7AA9@lizhi-Precision-Tower-5810>
Date: Wed, 16 Jul 2025 16:05:59 -0400
From: Frank Li <Frank.li@....com>
To: Wei Fang <wei.fang@....com>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
richardcochran@...il.com, claudiu.manoil@....com,
vladimir.oltean@....com, xiaoning.wang@....com,
andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, vadim.fedorenko@...ux.dev,
shawnguo@...nel.org, s.hauer@...gutronix.de, festevam@...il.com,
fushi.peng@....com, devicetree@...r.kernel.org,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
imx@...ts.linux.dev, kernel@...gutronix.de
Subject: Re: [PATCH v2 net-next 04/14] ptp: netc: add PTP_CLK_REQ_PPS support
On Wed, Jul 16, 2025 at 03:31:01PM +0800, Wei Fang wrote:
> The NETC Times is able to generate the PPS event, so add PTP_CLK_REQ_PPS
> support. In addition, if there is a time drift when PPS is enabled, the
> PPS event will not be generated at an integral second of PHC. Based on
> the suggestion from IP team, FIPER should be disabled before adjusting
> the hardware time and then rearm ALARM after the time adjustment to make
> the next PPS event be generated at an integral second of PHC. Finally,
> re-enable FIPER.
Add PTP_CLK_REQ_PPS supports.
The suggested steps by IP team if time drift happen:
1: Disable FIPER before adjusting the hardware time
2: rearm ALARM after the time adjustment to make ...
3: re-enable FIPER.
>
> Signed-off-by: Wei Fang <wei.fang@....com>
>
> ---
> v2 changes:
> 1. Refine the subject and the commit message
> 2. Add a comment to netc_timer_enable_pps()
> 3. Remove the "nxp,pps-channel" logic from the driver
> ---
> drivers/ptp/ptp_netc.c | 176 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 175 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ptp/ptp_netc.c b/drivers/ptp/ptp_netc.c
> index 82cb1e6a0fe9..e39605c5b73b 100644
> --- a/drivers/ptp/ptp_netc.c
> +++ b/drivers/ptp/ptp_netc.c
> @@ -24,6 +24,8 @@
> #define TMR_ALARM1P BIT(31)
>
> #define NETC_TMR_TEVENT 0x0084
> +#define TMR_TEVNET_PPEN(i) BIT(7 - (i))
> +#define TMR_TEVENT_PPEN_ALL GENMASK(7, 5)
> #define TMR_TEVENT_ALM1EN BIT(16)
> #define TMR_TEVENT_ALM2EN BIT(17)
>
> @@ -39,9 +41,15 @@
> #define NETC_TMR_ALARM_L(i) (0x00b8 + (i) * 8)
> #define NETC_TMR_ALARM_H(i) (0x00bc + (i) * 8)
>
> +/* i = 0, 1, 2. i indicates the index of TMR_FIPER. */
> +#define NETC_TMR_FIPER(i) (0x00d0 + (i) * 4)
> +
> #define NETC_TMR_FIPER_CTRL 0x00dc
> #define FIPER_CTRL_DIS(i) (BIT(7) << (i) * 8)
> #define FIPER_CTRL_PG(i) (BIT(6) << (i) * 8)
> +#define FIPER_CTRL_FS_ALARM(i) (BIT(5) << (i) * 8)
> +#define FIPER_CTRL_PW(i) (GENMASK(4, 0) << (i) * 8)
> +#define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i))
>
> #define NETC_TMR_CUR_TIME_L 0x00f0
> #define NETC_TMR_CUR_TIME_H 0x00f4
> @@ -51,6 +59,9 @@
> #define NETC_TMR_FIPER_NUM 3
> #define NETC_TMR_DEFAULT_PRSC 2
> #define NETC_TMR_DEFAULT_ALARM GENMASK_ULL(63, 0)
> +#define NETC_TMR_DEFAULT_PPS_CHANNEL 0
> +#define NETC_TMR_DEFAULT_FIPER GENMASK(31, 0)
> +#define NETC_TMR_FIPER_MAX_PW GENMASK(4, 0)
>
> /* 1588 timer reference clock source select */
> #define NETC_TMR_CCM_TIMER1 0 /* enet_timer1_clk_root, from CCM */
> @@ -75,6 +86,8 @@ struct netc_timer {
> u64 period;
>
> int irq;
> + u8 pps_channel;
> + bool pps_enabled;
> };
>
> #define netc_timer_rd(p, o) netc_read((p)->base + (o))
> @@ -152,6 +165,147 @@ static void netc_timer_alarm_write(struct netc_timer *priv,
> netc_timer_wr(priv, NETC_TMR_ALARM_H(index), alarm_h);
> }
>
> +static u32 netc_timer_get_integral_period(struct netc_timer *priv)
> +{
> + u32 tmr_ctrl, integral_period;
> +
> + tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
> + integral_period = FIELD_GET(TMR_CTRL_TCLK_PERIOD, tmr_ctrl);
> +
> + return integral_period;
> +}
> +
> +static u32 netc_timer_calculate_fiper_pw(struct netc_timer *priv,
> + u32 fiper)
> +{
> + u64 divisor, pulse_width;
> +
> + /* Set the FIPER pulse width to half FIPER interval by default.
> + * pulse_width = (fiper / 2) / TMR_GCLK_period,
> + * TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq,
> + * TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz,
> + * so pulse_width = fiper * clk_freq / (2 * NSEC_PER_SEC * oclk_prsc).
> + */
> + divisor = mul_u32_u32(2000000000U, priv->oclk_prsc);
is it 2*PSEC_PER_SEC ?
Frank
> + pulse_width = div64_u64(mul_u32_u32(fiper, priv->clk_freq), divisor);
> +
> + /* The FIPER_PW field only has 5 bits, need to update oclk_prsc */
> + if (pulse_width > NETC_TMR_FIPER_MAX_PW)
> + pulse_width = NETC_TMR_FIPER_MAX_PW;
> +
> + return pulse_width;
> +}
> +
> +static void netc_timer_set_pps_alarm(struct netc_timer *priv, int channel,
> + u32 integral_period)
> +{
> + u64 alarm;
> +
> + /* Get the alarm value */
> + alarm = netc_timer_cur_time_read(priv) + NSEC_PER_MSEC;
> + alarm = roundup_u64(alarm, NSEC_PER_SEC);
> + alarm = roundup_u64(alarm, integral_period);
> +
> + netc_timer_alarm_write(priv, alarm, 0);
> +}
> +
> +/* Note that users should not use this API to output PPS signal on
> + * external pins, because PTP_CLK_REQ_PPS trigger internal PPS event
> + * for input into kernel PPS subsystem. See:
> + * https://lore.kernel.org/r/20201117213826.18235-1-a.fatoum@pengutronix.de
> + */
> +static int netc_timer_enable_pps(struct netc_timer *priv,
> + struct ptp_clock_request *rq, int on)
> +{
> + u32 tmr_emask, fiper, fiper_ctrl;
> + u8 channel = priv->pps_channel;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> +
> + tmr_emask = netc_timer_rd(priv, NETC_TMR_TEMASK);
> + fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
> +
> + if (on) {
> + u32 integral_period, fiper_pw;
> +
> + if (priv->pps_enabled)
> + goto unlock_spinlock;
> +
> + integral_period = netc_timer_get_integral_period(priv);
> + fiper = NSEC_PER_SEC - integral_period;
> + fiper_pw = netc_timer_calculate_fiper_pw(priv, fiper);
> + fiper_ctrl &= ~(FIPER_CTRL_DIS(channel) | FIPER_CTRL_PW(channel) |
> + FIPER_CTRL_FS_ALARM(channel));
> + fiper_ctrl |= FIPER_CTRL_SET_PW(channel, fiper_pw);
> + tmr_emask |= TMR_TEVNET_PPEN(channel);
> + priv->pps_enabled = true;
> + netc_timer_set_pps_alarm(priv, channel, integral_period);
> + } else {
> + if (!priv->pps_enabled)
> + goto unlock_spinlock;
> +
> + fiper = NETC_TMR_DEFAULT_FIPER;
> + tmr_emask &= ~TMR_TEVNET_PPEN(channel);
> + fiper_ctrl |= FIPER_CTRL_DIS(channel);
> + priv->pps_enabled = false;
> + }
> +
> + netc_timer_wr(priv, NETC_TMR_TEMASK, tmr_emask);
> + netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper);
> + netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
> +
> +unlock_spinlock:
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return 0;
> +}
> +
> +static void netc_timer_disable_pps_fiper(struct netc_timer *priv)
> +{
> + u32 fiper = NETC_TMR_DEFAULT_FIPER;
> + u8 channel = priv->pps_channel;
> + u32 fiper_ctrl;
> +
> + if (!priv->pps_enabled)
> + return;
> +
> + fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
> + fiper_ctrl |= FIPER_CTRL_DIS(channel);
> + netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper);
> + netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
> +}
> +
> +static void netc_timer_enable_pps_fiper(struct netc_timer *priv)
> +{
> + u32 fiper_ctrl, integral_period, fiper;
> + u8 channel = priv->pps_channel;
> +
> + if (!priv->pps_enabled)
> + return;
> +
> + integral_period = netc_timer_get_integral_period(priv);
> + fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
> + fiper_ctrl &= ~FIPER_CTRL_DIS(channel);
> + fiper = NSEC_PER_SEC - integral_period;
> + netc_timer_set_pps_alarm(priv, channel, integral_period);
> + netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper);
> + netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
> +}
> +
> +static int netc_timer_enable(struct ptp_clock_info *ptp,
> + struct ptp_clock_request *rq, int on)
> +{
> + struct netc_timer *priv = ptp_to_netc_timer(ptp);
> +
> + switch (rq->type) {
> + case PTP_CLK_REQ_PPS:
> + return netc_timer_enable_pps(priv, rq, on);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static void netc_timer_adjust_period(struct netc_timer *priv, u64 period)
> {
> u32 fractional_period = lower_32_bits(period);
> @@ -164,8 +318,11 @@ static void netc_timer_adjust_period(struct netc_timer *priv, u64 period)
> old_tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
> tmr_ctrl = u32_replace_bits(old_tmr_ctrl, integral_period,
> TMR_CTRL_TCLK_PERIOD);
> - if (tmr_ctrl != old_tmr_ctrl)
> + if (tmr_ctrl != old_tmr_ctrl) {
> + netc_timer_disable_pps_fiper(priv);
> netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
> + netc_timer_enable_pps_fiper(priv);
> + }
>
> netc_timer_wr(priv, NETC_TMR_ADD, fractional_period);
>
> @@ -191,6 +348,8 @@ static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta)
>
> spin_lock_irqsave(&priv->lock, flags);
>
> + netc_timer_disable_pps_fiper(priv);
> +
> tmr_off = netc_timer_offset_read(priv);
> if (delta < 0 && tmr_off < abs(delta)) {
> delta += tmr_off;
> @@ -205,6 +364,8 @@ static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta)
> netc_timer_offset_write(priv, tmr_off);
> }
>
> + netc_timer_enable_pps_fiper(priv);
> +
> spin_unlock_irqrestore(&priv->lock, flags);
>
> return 0;
> @@ -239,8 +400,12 @@ static int netc_timer_settime64(struct ptp_clock_info *ptp,
> unsigned long flags;
>
> spin_lock_irqsave(&priv->lock, flags);
> +
> + netc_timer_disable_pps_fiper(priv);
> netc_timer_offset_write(priv, 0);
> netc_timer_cnt_write(priv, ns);
> + netc_timer_enable_pps_fiper(priv);
> +
> spin_unlock_irqrestore(&priv->lock, flags);
>
> return 0;
> @@ -267,10 +432,12 @@ static const struct ptp_clock_info netc_timer_ptp_caps = {
> .max_adj = 500000000,
> .n_alarm = 2,
> .n_pins = 0,
> + .pps = 1,
> .adjfine = netc_timer_adjfine,
> .adjtime = netc_timer_adjtime,
> .gettimex64 = netc_timer_gettimex64,
> .settime64 = netc_timer_settime64,
> + .enable = netc_timer_enable,
> };
>
> static void netc_timer_init(struct netc_timer *priv)
> @@ -429,6 +596,7 @@ static int netc_timer_parse_dt(struct netc_timer *priv)
> static irqreturn_t netc_timer_isr(int irq, void *data)
> {
> struct netc_timer *priv = data;
> + struct ptp_clock_event event;
> u32 tmr_event, tmr_emask;
> unsigned long flags;
>
> @@ -444,6 +612,11 @@ static irqreturn_t netc_timer_isr(int irq, void *data)
> if (tmr_event & TMR_TEVENT_ALM2EN)
> netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 1);
>
> + if (tmr_event & TMR_TEVENT_PPEN_ALL) {
> + event.type = PTP_CLOCK_PPS;
> + ptp_clock_event(priv->clock, &event);
> + }
> +
> /* Clear interrupts status */
> netc_timer_wr(priv, NETC_TMR_TEVENT, tmr_event);
>
> @@ -506,6 +679,7 @@ static int netc_timer_probe(struct pci_dev *pdev,
>
> priv->caps = netc_timer_ptp_caps;
> priv->oclk_prsc = NETC_TMR_DEFAULT_PRSC;
> + priv->pps_channel = NETC_TMR_DEFAULT_PPS_CHANNEL;
> priv->phc_index = -1; /* initialize it as an invalid index */
> spin_lock_init(&priv->lock);
>
> --
> 2.34.1
>
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