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Message-ID: <aHkqtoNCJvorNnSq@67d05fca9368>
Date: Thu, 17 Jul 2025 16:54:14 +0000
From: Subbaraya Sundeep <sbhatta@...vell.com>
To: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
CC: <andrew+netdev@...n.ch>, <davem@...emloft.net>, <edumazet@...gle.com>,
<kuba@...nel.org>, <pabeni4redhat.com@...a-0016f401.pphosted.com>,
<horms@...nel.org>, <gakula@...vell.com>, <hkelam@...vell.com>,
<bbhushan2@...vell.com>, <jerinj@...vell.com>, <lcherian@...vell.com>,
<sgoutham@...vell.com>, <netdev@...r.kernel.org>
Subject: Re: [net-next PATCH v2 01/11] octeontx2-af: Simplify context writing
and reading to hardware
On 2025-07-16 at 09:24:07, Michal Swiatkowski (michal.swiatkowski@...ux.intel.com) wrote:
> On Tue, Jul 15, 2025 at 10:31:54PM +0530, Subbaraya Sundeep wrote:
> > Simplify NIX context reading and writing by using hardware
> > maximum context size instead of using individual sizes of
> > each context type.
> >
> > Signed-off-by: Subbaraya Sundeep <sbhatta@...vell.com>
> > ---
> > .../ethernet/marvell/octeontx2/af/rvu_nix.c | 46 ++++++++++---------
> > .../marvell/octeontx2/af/rvu_struct.h | 7 ++-
> > 2 files changed, 30 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > index bdf4d852c15d..48d44911b663 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > @@ -17,6 +17,8 @@
> > #include "lmac_common.h"
> > #include "rvu_npc_hash.h"
> >
> > +#define NIX_MAX_CTX_SIZE 128
> > +
>
> [...]
>
> >
> > return 0;
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > index 0596a3ac4c12..8a66f53a7658 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > @@ -370,6 +370,8 @@ struct nix_cq_ctx_s {
> > u64 qsize : 4;
> > u64 cq_err_int : 8;
> > u64 cq_err_int_ena : 8;
> > + /* Ensure all context sizes are minimum 128 bytes */
> > + u64 padding[12];
> > };
> >
> > /* CN10K NIX Receive queue context structure */
> > @@ -672,7 +674,8 @@ struct nix_sq_ctx_s {
> > struct nix_rsse_s {
> > uint32_t rq : 20;
> > uint32_t reserved_20_31 : 12;
> > -
> > + /* Ensure all context sizes are minimum 128 bytes */
> > + u64 padding[15];
> > };
> >
> > /* NIX receive multicast/mirror entry structure */
> > @@ -684,6 +687,8 @@ struct nix_rx_mce_s {
> > uint64_t rsvd_31_24 : 8;
> > uint64_t pf_func : 16;
> > uint64_t next : 16;
> > + /* Ensure all context sizes are minimum 128 bytes */
> > + u64 padding[15];
> > };
>
> To be sure that each used structures are correct size you can
> use static assertion, sth like:
> static_assert((NIC_MAX_CTX_SIZE) == sizeof(struct X))
>
> Thanks
>
Sure will do it.
Thanks,
Sundeep
> >
> > enum nix_band_prof_layers {
> > --
> > 2.34.1
> >
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