Message-ID: <20250721193545.GA1119033-robh@kernel.org>
Date: Mon, 21 Jul 2025 14:35:45 -0500
From: Rob Herring <robh@...nel.org>
To: Luo Jie <quic_luoj@...cinc.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Lei Wei <quic_leiwei@...cinc.com>,
	Suruchi Agarwal <quic_suruchia@...cinc.com>,
	Pavithra R <quic_pavir@...cinc.com>,
	Simon Horman <horms@...nel.org>, Jonathan Corbet <corbet@....net>,
	Kees Cook <kees@...nel.org>,
	"Gustavo A. R. Silva" <gustavoars@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	linux-arm-msm@...r.kernel.org, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-doc@...r.kernel.org, linux-hardening@...r.kernel.org,
	quic_kkumarcs@...cinc.com, quic_linchen@...cinc.com
Subject: Re: [PATCH net-next v6 01/14] dt-bindings: net: Add PPE for Qualcomm
 IPQ9574 SoC

On Sun, Jul 20, 2025 at 06:57:08PM +0800, Luo Jie wrote:
> The PPE (packet process engine) hardware block is available in Qualcomm
> IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in
> the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which
> are used to connect with external PHY devices by PCS. It includes an L2
> switch function for bridging packets among the 6 ethernet ports and the
> CPU port. The CPU port enables packet transfer between the ethernet ports
> and the ARM cores in the SoC, using the ethernet DMA.
> 
> The PPE also includes packet processing offload capabilities for various
> networking functions such as route and bridge flows, VLANs, different
> tunnel protocols and VPN.
> 
> The PPE switch is modeled according to the ethernet switch schema, with
> additional properties defined for the switch node for interrupts, clocks,
> resets, interconnects and Ethernet DMA. The switch port node is extended
> with additional properties for clocks and resets.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
>  .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml  | 529 +++++++++++++++++++++
>  1 file changed, 529 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
> new file mode 100644
> index 000000000000..d48169a8ba7c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
> @@ -0,0 +1,529 @@
> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ packet process engine (PPE)
> +
> +maintainers:
> +  - Luo Jie <quic_luoj@...cinc.com>
> +  - Lei Wei <quic_leiwei@...cinc.com>
> +  - Suruchi Agarwal <quic_suruchia@...cinc.com>
> +  - Pavithra R <quic_pavir@...cinc.com>
> +
> +description: |
> +  The Ethernet functionality in the PPE (Packet Process Engine) is comprised
> +  of three components, the switch core, port wrapper and Ethernet DMA.
> +
> +  The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
> +  two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet
> +  port to host CPU communication using Ethernet DMA. The other is used
> +  communicating to the EIP engine which is used for IPsec offload. On the
> +  IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external
> +  Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue
> +  Management) and SCH (Scheduler) modules for supporting the packet processing.
> +
> +  The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS)
> +  supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
> +  are 3 UNIPHY (PCS) instances supported on the IPQ9574.
> +
> +  Ethernet DMA is used to transmit and receive packets between the six Ethernet
> +  ports and ARM host CPU.
> +
> +  The follow diagram shows the PPE hardware block along with its connectivity
> +  to the external hardware blocks such clock hardware blocks (CMNPLL, GCC,
> +  NSS clock controller) and ethernet PCS/PHY blocks. For depicting the PHY
> +  connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an
> +  example.
> +
> +           +---------+
> +           |  48 MHZ |
> +           +----+----+
> +                |(clock)
> +                v
> +           +----+----+
> +    +------| CMN PLL |
> +    |      +----+----+
> +    |           |(clock)
> +    |           v
> +    |      +----+----+           +----+----+  (clock) +----+----+
> +    |  +---|  NSSCC  |           |   GCC   |--------->|   MDIO  |
> +    |  |   +----+----+           +----+----+          +----+----+
> +    |  |        |(clock & reset)      |(clock)
> +    |  |        v                     v
> +    |  |   +----+---------------------+--+----------+----------+---------+
> +    |  |   |       +-----+               |EDMA FIFO |          | EIP FIFO|
> +    |  |   |       | SCH |               +----------+          +---------+
> +    |  |   |       +-----+                        |              |       |
> +    |  |   |  +------+   +------+               +-------------------+    |
> +    |  |   |  |  BM  |   |  QM  |  IPQ9574-PPE  |    L2/L3 Process  |    |
> +    |  |   |  +------+   +------+               +-------------------+    |
> +    |  |   |                                             |               |
> +    |  |   | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ |
> +    |  |   | |  MAC0 | |  MAC1 | |  MAC2 | |  MAC3 | | XGMAC4| |XGMAC5 | |
> +    |  |   | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ |
> +    |  |   |     |         |         |         |         |         |     |
> +    |  |   +-----+---------+---------+---------+---------+---------+-----+
> +    |  |         |         |         |         |         |         |
> +    |  |     +---+---------+---------+---------+---+ +---+---+ +---+---+
> +    +--+---->|                PCS0                 | |  PCS1 | | PCS2  |
> +    |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+
> +    |            |         |         |         |         |         |
> +    |        +---+---------+---------+---------+---+ +---+---+ +---+---+
> +    +------->|             QCA8075 PHY             | | PHY4  | | PHY5  |
> +     (clock) +-------------------------------------+ +-------+ +-------+
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,ipq9574-ppe
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PPE core clock from NSS clock controller
> +      - description: PPE APB (Advanced Peripheral Bus) clock from NSS clock controller
> +      - description: PPE ingress process engine clock from NSS clock controller
> +      - description: PPE BM, QM and scheduler clock from NSS clock controller

Drop 'from NSS clock controller'. That's outside the scope of this 
binding.

> +
> +  clock-names:
> +    items:
> +      - const: ppe
> +      - const: apb
> +      - const: ipe
> +      - const: btq
> +
> +  resets:
> +    maxItems: 1
> +    description: PPE reset, which is necessary before configuring PPE hardware
> +
> +  interrupts:
> +    maxItems: 1
> +    description: PPE switch miscellaneous interrupt
> +
> +  interconnects:
> +    items:
> +      - description: Clock path leading to PPE switch core function
> +      - description: Clock path leading to PPE register access
> +      - description: Clock path leading to QoS generation
> +      - description: Clock path leading to timeout reference
> +      - description: Clock path leading to NSS NOC from memory NOC
> +      - description: Clock path leading to memory NOC from NSS NOC
> +      - description: Clock path leading to enhanced memory NOC from NSS NOC

Clock path? This should be bus interconnect paths.

> +
> +  interconnect-names:
> +    items:
> +      - const: ppe
> +      - const: ppe_cfg
> +      - const: qos_gen
> +      - const: timeout_ref
> +      - const: nssnoc_memnoc
> +      - const: memnoc_nssnoc
> +      - const: memnoc_nssnoc_1
> +
> +  ethernet-dma:
> +    type: object
> +    additionalProperties: false
> +    description:
> +      EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM
> +      host CPU. There are 32 TX descriptor rings, 32 TX completion rings,
> +      24 RX descriptor rings and 8 RX fill rings supported.
> +
> +    properties:
> +      clocks:
> +        items:
> +          - description: EDMA system clock from NSS Clock Controller
> +          - description: EDMA APB (Advanced Peripheral Bus) clock from
> +              NSS Clock Controller
> +
> +      clock-names:
> +        items:
> +          - const: sys
> +          - const: apb
> +
> +      resets:
> +        maxItems: 1
> +        description: EDMA reset from NSS clock controller
> +
> +      interrupts:
> +        minItems: 65
> +        maxItems: 65
> +
> +      interrupt-names:
> +        minItems: 65
> +        maxItems: 65
> +        description:
> +          Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts.
> +          Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts.
> +          Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts.
> +          Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt.

items:
  oneOf:
    - pattern: '^txcmpl_([1-2]?[0-9]|3[01])$'
    - pattern: '^rxfill_[0-7]$'
    - pattern: '^rxdesc_(1?[0-9]|2[0-3])$'
    - const: misc

> +
> +    required:
> +      - clocks
> +      - clock-names
> +      - resets
> +      - interrupts
> +      - interrupt-names
> +
> +patternProperties:
> +  "^(ethernet-)?ports$":

New binding, does 'ethernet-' part need to be optional? No.

> +    patternProperties:
> +      "^ethernet-port@[1-6]+$":
> +        type: object
> +        unevaluatedProperties: false
> +        $ref: ethernet-switch-port.yaml#
> +
> +        properties:
> +          reg:
> +            minimum: 1
> +            maximum: 6
> +            description: PPE Ethernet port ID
> +
> +          clocks:
> +            items:
> +              - description: Port MAC clock from NSS clock controller
> +              - description: Port RX clock from NSS clock controller
> +              - description: Port TX clock from NSS clock controller
> +
> +          clock-names:
> +            items:
> +              - const: mac
> +              - const: rx
> +              - const: tx
> +
> +          resets:
> +            items:
> +              - description: Port MAC reset from NSS clock controller
> +              - description: Port RX reset from NSS clock controller
> +              - description: Port TX reset from NSS clock controller
> +
> +          reset-names:
> +            items:
> +              - const: mac
> +              - const: rx
> +              - const: tx
> +
> +        required:
> +          - reg
> +          - clocks
> +          - clock-names
> +          - resets
> +          - reset-names
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - interconnects
> +  - interconnect-names
> +  - ethernet-dma
> +
> +allOf:
> +  - $ref: ethernet-switch.yaml
> +
> +unevaluatedProperties: false

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