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Message-ID: <20250722162950.GO2459@horms.kernel.org>
Date: Tue, 22 Jul 2025 17:29:50 +0100
From: Simon Horman <horms@...nel.org>
To: Subbaraya Sundeep <sbhatta@...vell.com>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, gakula@...vell.com,
hkelam@...vell.com, bbhushan2@...vell.com, jerinj@...vell.com,
lcherian@...vell.com, sgoutham@...vell.com, netdev@...r.kernel.org
Subject: Re: [net-next PATCH v3 01/11] octeontx2-af: Simplify context writing
and reading to hardware
On Tue, Jul 22, 2025 at 05:27:43PM +0100, Simon Horman wrote:
> On Thu, Jul 17, 2025 at 10:37:33PM +0530, Subbaraya Sundeep wrote:
> > Simplify NIX context reading and writing by using hardware
> > maximum context size instead of using individual sizes of
> > each context type.
> >
> > Signed-off-by: Subbaraya Sundeep <sbhatta@...vell.com>
>
> ...
>
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > index 0596a3ac4c12..1097c86fdc46 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
> > @@ -13,6 +13,8 @@
> >
> > #define RVU_MULTI_BLK_VER 0x7ULL
> >
> > +#define NIX_MAX_CTX_SIZE 128
> > +
> > /* RVU Block Address Enumeration */
> > enum rvu_block_addr_e {
> > BLKADDR_RVUM = 0x0ULL,
> > @@ -370,8 +372,12 @@ struct nix_cq_ctx_s {
> > u64 qsize : 4;
> > u64 cq_err_int : 8;
> > u64 cq_err_int_ena : 8;
> > + /* Ensure all context sizes are minimum 128 bytes */
>
> Would this be better phrased as follows?
>
> /* Ensure all context sizes are 128 bytes */
>
> > + u64 padding[12];
> > };
> >
> > +static_assert(sizeof(struct nix_cq_ctx_s) == NIX_MAX_CTX_SIZE);
>
> I would suggest adding +static_assert() for all the
> drivers that you expect to be NIX_MAX_CTX_SIZE.
>
> So also:
> - struct nix_rq_ctx_s
> - struct nix_sq_ctx_s
> - struct nix_bandprof_s
Likewise for new structures added by subsequent patches.
...
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