netdev - Re: [PATCH V2 1/4] dmaengine: Add support to configure and read IRQ coalescing parameters

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Message-ID: <aICPiS1_ITwELrxq@vaman>
Date: Wed, 23 Jul 2025 13:00:17 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Suraj Gupta <suraj.gupta2@....com>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, kuba@...nel.org,
	pabeni@...hat.com, michal.simek@....com,
	radhey.shyam.pandey@....com, netdev@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	dmaengine@...r.kernel.org, harini.katakam@....com
Subject: Re: [PATCH V2 1/4] dmaengine: Add support to configure and read IRQ
 coalescing parameters

On 10-07-25, 15:42, Suraj Gupta wrote:
> Interrupt coalescing is a mechanism to reduce the number of hardware
> interrupts triggered ether until a certain amount of work is pending,
> or a timeout timer triggers. Tuning the interrupt coalesce settings
> involves adjusting the amount of work and timeout delay.
> Many DMA controllers support to configure coalesce count and delay.
> Add support to configure them via dma_slave_config and read
> using dma_slave_caps.
> 
> Signed-off-by: Suraj Gupta <suraj.gupta2@....com>
> ---
>  include/linux/dmaengine.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index bb146c5ac3e4..c7c1adb8e571 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -431,6 +431,9 @@ enum dma_slave_buswidth {
>   * @peripheral_config: peripheral configuration for programming peripheral
>   * for dmaengine transfer
>   * @peripheral_size: peripheral configuration buffer size
> + * @coalesce_cnt: Maximum number of transfers before receiving an interrupt.
> + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer
> + * is completed.
>   *
>   * This struct is passed in as configuration data to a DMA engine
>   * in order to set up a certain channel for DMA transport at runtime.
> @@ -457,6 +460,8 @@ struct dma_slave_config {
>  	bool device_fc;
>  	void *peripheral_config;
>  	size_t peripheral_size;
> +	u32 coalesce_cnt;
> +	u32 coalesce_usecs;
>  };
>  
>  /**
> @@ -507,6 +512,9 @@ enum dma_residue_granularity {
>   * @residue_granularity: granularity of the reported transfer residue
>   * @descriptor_reuse: if a descriptor can be reused by client and
>   * resubmitted multiple times
> + * @coalesce_cnt: Maximum number of transfers before receiving an interrupt.
> + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer
> + * is completed.
>   */
>  struct dma_slave_caps {
>  	u32 src_addr_widths;
> @@ -520,6 +528,8 @@ struct dma_slave_caps {
>  	bool cmd_terminate;
>  	enum dma_residue_granularity residue_granularity;
>  	bool descriptor_reuse;
> +	u32 coalesce_cnt;
> +	u32 coalesce_usecs;

Why not selectively set interrupts for the descriptor. The dma
descriptors are in order, so one a descriptor is notified and complete,
you can also complete the descriptors before that. I would suggest to
use that rather than define a new interface for this

-- 
~Vinod