Message-Id: <DBOD5ICCVSL1.23R4QZPSFPVSM@kernel.org>
Date: Tue, 29 Jul 2025 09:33:57 +0200
From: "Michael Walle" <mwalle@...nel.org>
To: "Andrew Lunn" <andrew@...n.ch>
Cc: "Andrew Lunn" <andrew+netdev@...n.ch>, "David S . Miller"
 <davem@...emloft.net>, "Eric Dumazet" <edumazet@...gle.com>, "Jakub
 Kicinski" <kuba@...nel.org>, "Paolo Abeni" <pabeni@...hat.com>, "Roger
 Quadros" <rogerq@...nel.org>, "Simon Horman" <horms@...nel.org>, "Siddharth
 Vadapalli" <s-vadapalli@...com>, "Matthias Schiffer"
 <matthias.schiffer@...tq-group.com>, "Maxime Chevallier"
 <maxime.chevallier@...tlin.com>, <netdev@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next] Revert "net: ethernet: ti: am65-cpsw: fixup
 PHY mode for fixed RGMII TX delay"

On Mon Jul 28, 2025 at 4:41 PM CEST, Andrew Lunn wrote:
> On Mon, Jul 28, 2025 at 08:49:38AM +0200, Michael Walle wrote:
> > This reverts commit ca13b249f291f4920466638d1adbfb3f9c8db6e9.
> > 
> > This patch breaks the transmit path on an AM67A/J722S. This SoC has an
> > (undocumented) configurable delay (CTRL_MMR0_CFG0_ENET1_CTRL, bit 4).
>
> Is this undocumented register only on the AM67A/J722S?

I've looked at the AM65x TRM (search for MMR0 or RGMII_ID_MODE),
which reads that bit 4 is r/w but only '0' is documented as
'internal transmit delay', value '1' is called "reserved".

I couldn't find anything in the AM64x TRM. Didn't look further.

There has to be a reason why TI states that TX delay is always on
and don't document that bit. OTOH, they wrote code to serve that bit
in u-boot. Sigh. Someone from TI have to chime in here to shed some
light to this.

> The patch being reverted says:
>
>    All am65-cpsw controllers have a fixed TX delay
>
> So we have some degree of contradiction here.

I've digged through the old thread and Matthias just references the
datasheet saying it is fixed. Matthias, could you actually try to
set/read this bit? I'm not sure it is really read-only.

> > The u-boot driver (net/ti/am65-cpsw-nuss.c) will configure the delay in
> > am65_cpsw_gmii_sel_k3(). If the u-boot device tree uses rgmii-id this
> > patch will break the transmit path because it will disable the PHY delay
> > on the transmit path, but the bootloader has already disabled the MAC
> > delay, hence there will be no delay at all.
>
> We have maybe 8 weeks to fix this, before it makes it into a released
> kernel. So rather than revert, i would prefer to extend the patch to
> make it work with all variants of the SoC.
>
> Is CTRL_MMR0_CFG0_ENET1_CTRL in the Ethernet address space?

No, that register is part of the global configuration space (search
for phy_gmii_sel in the k3-am62p-j722s-common-main.dtsi), but is
modeled after a PHY (not a network PHY). And actually, I've just
found out that the PHY driver for that will serve the rgmii_id bit
if .features has PHY_GMII_SEL_RGMII_ID_MODE set. So there is already
a whitelist (although it's wrong at the moment, because the J722S
SoC is not listed as having it). As a side note, the j722s also
doesn't have it's own SoC specific compatible it is reusing the
am654-phy-gmii-sel compatible. That might or might not bite us now..

I digress..

> Would it be possible for the MAC driver to read it, and know if the delay has
> been disabled? The switch statement can then be made conditional?
>
> If this register actually exists on all SoC variants, can we just
> globally disable it, and remove the switch statement?

Given that all the handling is in the PHY subsystem I don't know.
You'd have to ask the PHY if it supports that, before patching the
phy-interface-mode - before attaching the network PHY I guess?

If we want to just disable (and I assume with disable you mean
disable the MAC delay) it: the PHY is optional, not sure every SoC
will have one. And also, the reset default is exactly the opposite
and TI says it's fixed to the opposite and there has to be a reason
for that.

Sounds like a real mess to me.

-michael

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