Message-Id: <DBOEPHG2V5WY.Q47MW1V5ZJZE@kernel.org>
Date: Tue, 29 Jul 2025 10:47:04 +0200
From: "Michael Walle" <mwalle@...nel.org>
To: "Matthias Schiffer" <matthias.schiffer@...tq-group.com>, "Andrew Lunn"
 <andrew@...n.ch>, "Nishanth Menon" <nm@...com>, "Vignesh Raghavendra"
 <vigneshr@...com>, "Tero Kristo" <kristo@...nel.org>
Cc: "Andrew Lunn" <andrew+netdev@...n.ch>, "David S . Miller"
 <davem@...emloft.net>, "Eric Dumazet" <edumazet@...gle.com>, "Jakub
 Kicinski" <kuba@...nel.org>, "Paolo Abeni" <pabeni@...hat.com>, "Roger
 Quadros" <rogerq@...nel.org>, "Simon Horman" <horms@...nel.org>, "Siddharth
 Vadapalli" <s-vadapalli@...com>, "Maxime Chevallier"
 <maxime.chevallier@...tlin.com>, <netdev@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>, <linux@...tq-group.com>
Subject: Re: [PATCH net-next] Revert "net: ethernet: ti: am65-cpsw: fixup
 PHY mode for fixed RGMII TX delay"

Hi,

> > > The patch being reverted says:
> > > 
> > >    All am65-cpsw controllers have a fixed TX delay
> > > 
> > > So we have some degree of contradiction here.
> > 
> > I've digged through the old thread and Matthias just references the
> > datasheet saying it is fixed. Matthias, could you actually try to
> > set/read this bit? I'm not sure it is really read-only.
>
> I just referred to the datasheets of various K3 SoCs, I did not try modifying
> the reserved bits.

So can you try to modify them?

> > > > The u-boot driver (net/ti/am65-cpsw-nuss.c) will configure the delay in
> > > > am65_cpsw_gmii_sel_k3(). If the u-boot device tree uses rgmii-id this
> > > > patch will break the transmit path because it will disable the PHY delay
> > > > on the transmit path, but the bootloader has already disabled the MAC
> > > > delay, hence there will be no delay at all.
>
> I have a patch that removes this piece of U-Boot code and had intended to submit
> that soon to align the U-Boot driver with Linux again. I'll hold off until we
> know how the solution in Linux is going to look.

That doesn't fix older bootloaders though. So in linux we still have
to work around that.

Although I don't get it why you want to remove that feature.

> > > We have maybe 8 weeks to fix this, before it makes it into a released
> > > kernel. So rather than revert, i would prefer to extend the patch to
> > > make it work with all variants of the SoC.
> > > 
> > > Is CTRL_MMR0_CFG0_ENET1_CTRL in the Ethernet address space?
> > 
> > No, that register is part of the global configuration space (search
> > for phy_gmii_sel in the k3-am62p-j722s-common-main.dtsi), but is
> > modeled after a PHY (not a network PHY). And actually, I've just
> > found out that the PHY driver for that will serve the rgmii_id bit
> > if .features has PHY_GMII_SEL_RGMII_ID_MODE set. So there is already
> > a whitelist (although it's wrong at the moment, because the J722S
> > SoC is not listed as having it). As a side note, the j722s also
> > doesn't have it's own SoC specific compatible it is reusing the
> > am654-phy-gmii-sel compatible. That might or might not bite us now..
> > 
> > I digress..
> > 
> > > Would it be possible for the MAC driver to read it, and know if the delay has
> > > been disabled? The switch statement can then be made conditional?
> > > 
> > > If this register actually exists on all SoC variants, can we just
> > > globally disable it, and remove the switch statement?
>
> If we just remove the switch statement, thus actually supporting all the
> different delay modes, we're back at the point where there is no way for the
> driver to determine whether rgmii-rxid is supposed to be interpreted correctly
> or not (currently all Device Trees using this driver require the old/incorrect
> interpretation for Ethernet to work).

I can't follow you here. Are you assuming that the TX delay is
fixed? For me, that's still the culprit. Is that a fair assumption?
And only TI can tell us.

> > Given that all the handling is in the PHY subsystem I don't know.
> > You'd have to ask the PHY if it supports that, before patching the
> > phy-interface-mode - before attaching the network PHY I guess?
>
> The previous generation of the CPSW IP handles this in
> drivers/net/ethernet/ti/cpsw-phy-sel.c, which is just a custom platform device
> referenced by the MAC node. The code currently (partially) implements the
> old/incorrect interpretation for phy-mode, enabling the delay on the MAC side
> for PHY_INTERFACE_MODE_RGMII.
>
> > 
> > If we want to just disable (and I assume with disable you mean
> > disable the MAC delay) it: the PHY is optional, not sure every SoC
> > will have one. And also, the reset default is exactly the opposite
> > and TI says it's fixed to the opposite and there has to be a reason
> > for that.
>
> My preference would be to unconditionally enable the MAC-side delay on Linux to
> align with the reset default and what the datasheet claims is the only supported
> mode, but let's hear what the TI folks think about this.

Which goes against Andrew's "lets to all the delays in the PHY". We
have rgmii-id in our AM67A based board and we've actually measured
the signals with and without the MAC delay.

Last week, I've also opened an e2e forum case, maybe we get some
more insights. Funny enough, TI seem to have a different register
description where this bit is described.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1544031/am67a-internal-rgmii-delay/

-michael

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