netdev - Re: Aquantia PHY in OCSGMII mode?

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Message-ID: <aIvDcxeBPhHADDik@shell.armlinux.org.uk>
Date: Thu, 31 Jul 2025 20:26:43 +0100
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Vladimir Oltean <olteanv@...il.com>
Cc: Alexander Wilhelm <alexander.wilhelm@...termo.com>,
	Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: Aquantia PHY in OCSGMII mode?

On Thu, Jul 31, 2025 at 08:16:42PM +0300, Vladimir Oltean wrote:
> Hi Alexander,
> 
> On Thu, Jul 31, 2025 at 04:59:09PM +0200, Alexander Wilhelm wrote:
> > Hello devs,
> > 
> > I'm fairly new to Ethernet PHY drivers and would appreciate your help. I'm
> > working with the Aquantia AQR115 PHY. The existing driver already supports the
> > AQR115C, so I reused that code for the AQR115, assuming minimal differences. My
> > goal is to enable 2.5G link speed. The PHY supports OCSGMII mode, which seems to
> > be non-standard.
> > 
> > * Is it possible to use this mode with the current driver?
> > * If yes, what would be the correct DTS entry?
> > * If not, I’d be willing to implement support. Could you suggest a good starting point?
> > 
> > Any hints or guidance would be greatly appreciated.
> > 
> > 
> > Best regards
> > Alexander Wilhelm
> > 
> 
> In addition to what Andrew and Russell said:
> 
> The Aquantia PHY driver is a bit unlike other PHY drivers, in that it
> prefers not to change the hardware configuration, and work with the
> provisioning of the firmware.

I'll state here that this is a design decision of the PHY driver.
It is possible to reconfigure the PHY (I have code in the PHY
driver to do it, so I can test the module on the Armada 388 based
Clearfog patform.

Essentially, in aqr107_fill_interface_modes() I do this:

+       phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, MDIO_CTRL1_LPOWER);
+       mdelay(10);
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x31a, 2);
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10M,
+                     VEND1_GLOBAL_CFG_SGMII_AN |
+                     VEND1_GLOBAL_CFG_SERDES_MODE_SGMII);
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_100M,
+                     VEND1_GLOBAL_CFG_SGMII_AN |
+                     VEND1_GLOBAL_CFG_SERDES_MODE_SGMII);
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_1G,
+                     VEND1_GLOBAL_CFG_SGMII_AN |
+                     VEND1_GLOBAL_CFG_SERDES_MODE_SGMII);
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G,
+                     VEND1_GLOBAL_CFG_SGMII_AN |
+                     VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII);
+       phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
+                          MDIO_CTRL1_LPOWER);

with:

 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI       0
 #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII     3
 #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII   4
+#define VEND1_GLOBAL_CFG_SERDES_MODE_LOW_POWER 5
 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G     6
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI20G    7
+#define VEND1_GLOBAL_CFG_SGMII_AN              BIT(3)
+#define VEND1_GLOBAL_CFG_SERDES_SILENT         BIT(6)

and this works. So... we could actually reconfigure the PHY independent
of what was programmed into the firmware.

-- 
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