netdev - Re: [PATCH v24 1/1] mctp pcc: Implement MCTP over PCC Transport

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Message-ID: <5a061bbd-637b-41c1-a6a7-5a14e479e572@amperemail.onmicrosoft.com>
Date: Thu, 14 Aug 2025 13:56:38 -0400
From: Adam Young <admiyo@...eremail.onmicrosoft.com>
To: Jeremy Kerr <jk@...econstruct.com.au>, admiyo@...amperecomputing.com,
 Matt Johnston <matt@...econstruct.com.au>,
 Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
 Sudeep Holla <sudeep.holla@....com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>,
 Huisong Li <lihuisong@...wei.com>
Subject: Re: [PATCH v24 1/1] mctp pcc: Implement MCTP over PCC Transport

On 8/13/25 00:46, Jeremy Kerr wrote:
> And just confirming: the pcc header format is now all host-endian - or
> is that a firmware-specified endianness? (what happens if the OS may
> boot in either BE or LE? is that at all possible for any PCC-capable
> hardware, or are we otherwise guaranteed that we're the same endianness
> as the consumer?)

The specification does not specify endianess.  It is not addressed in 
the ACPI  PCC spec nor the MCTP over PCC spec. There does not seem  to 
be any endianess modifiers in any of the ACPI code base.  Thus I have 
removed any references to it.  Since PCC is on a single SOC with a 
shared memory setup, the endianess would have to be matched between both 
ends of the system or you would have memory corruption.