netdev - Re: [PATCH 3/3] net: j2: Introduce J-Core EMAC

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Message-ID: <ee607928-1845-47aa-90a1-6511decda49d@lunn.ch>
Date: Sat, 16 Aug 2025 02:18:22 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Artur Rojek <contact@...ur-rojek.eu>
Cc: Rob Landley <rob@...dley.net>, Jeff Dionne <jeff@...esemi.io>,
	John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] net: j2: Introduce J-Core EMAC

> Yes, it's an IC+ IP101ALF 10/100 Ethernet PHY [1]. It does have both MDC
> and MDIO pins connected, however I suspect that nothing really
> configures it, and it simply runs on default register values (which
> allow for valid operation in 100Mb/s mode, it seems). I doubt there is
> another IP core to handle MDIO, as this SoC design is optimized for
> minimal utilization of FPGA blocks. Does it make sense to you that a MAC
> could run without any access to an MDIO bus?

It can work like that. You will likely have problems if the link ever
negotiates 10Mbps or 100Mbps half duplex. You generally need to change
something in the MAC to support different speeds and duplex. Without
being able to talk to the PHY over MDIO you have no idea what it has
negotiated with the link peer.

	Andrew