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Message-ID: <20250818115754.1067154-2-irving-ch.lin@mediatek.com>
Date: Mon, 18 Aug 2025 19:57:29 +0800
From: irving.ch.lin <irving-ch.lin@...iatek.com>
To: Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Matthias Brugger
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Ulf Hansson
<ulf.hansson@...aro.org>, Richard Cochran <richardcochran@...il.com>
CC: Qiqi Wang <qiqi.wang@...iatek.com>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<linux-pm@...r.kernel.org>, <netdev@...r.kernel.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
<sirius.wang@...iatek.com>, <vince-wl.liu@...iatek.com>,
<jh.hsu@...iatek.com>, <irving-ch.lin@...iatek.com>
Subject: [PATCH 1/6] dt-bindings: clock: mediatek: Add new MT8189 clock
From: Irving-ch Lin <irving-ch.lin@...iatek.com>
Add the new binding documentation for system clock
and functional clock on MediaTek MT8189.
Signed-off-by: Irving-ch Lin <irving-ch.lin@...iatek.com>
---
.../bindings/clock/mediatek,mt8189-clock.yaml | 89 +++++++++++++++++++
.../clock/mediatek,mt8189-sys-clock.yaml | 58 ++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
new file mode 100644
index 000000000000..d0d887861a49
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8189-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT8189
+
+maintainers:
+ - Qiqi Wang <qiqi.wang@...iatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8189-camsys-main
+ - mediatek,mt8189-camsys-rawa
+ - mediatek,mt8189-camsys-rawb
+ - mediatek,mt8189-dbg-ao
+ - mediatek,mt8189-dem
+ - mediatek,mt8189-dispsys
+ - mediatek,mt8189-dvfsrc-top
+ - mediatek,mt8189-gce-d
+ - mediatek,mt8189-gce-m
+ - mediatek,mt8189-iic-wrap-e
+ - mediatek,mt8189-iic-wrap-en
+ - mediatek,mt8189-iic-wrap-s
+ - mediatek,mt8189-iic-wrap-ws
+ - mediatek,mt8189-imgsys1
+ - mediatek,mt8189-imgsys2
+ - mediatek,mt8189-infra-ao
+ - mediatek,mt8189-ipesys
+ - mediatek,mt8189-mdpsys
+ - mediatek,mt8189-mfgcfg
+ - mediatek,mt8189-mm-infra
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-scp-clk
+ - mediatek,mt8189-scp-i2c-clk
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+ - mediatek,mt8189-vdec-core
+ - mediatek,mt8189-venc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+
+ then:
+ required:
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ imp_iic_wrap_ws_clk@...21000 {
+ compatible = "mediatek,mt8189-iic-wrap-ws";
+ reg = <0 0x11b21000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
new file mode 100644
index 000000000000..0d27ff807e79
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8189-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT8189
+
+maintainers:
+ - Qiqi Wang <qiqi.wang@...iatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes -->
+ clock gate
+
+ The apmixedsys provides most of PLLs which generated from SoC 26m.
+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+ The mcusys provides mux control to select the clock source in AP MCU.
+ The device nodes also provide the system control capacity for configuration.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8189-apmixedsys
+ - mediatek,mt8189-topckgen
+ - mediatek,mt8189-vlp-ckgen
+ - mediatek,mt8189-vlp-ao-ckgen
+ - mediatek,mt8189-vlpcfg-reg-bus
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ topckgen_clk@...00000 {
+ compatible = "mediatek,mt8189-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
--
2.45.2
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