lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250820171302.324142-8-ariel.dalessandro@collabora.com>
Date: Wed, 20 Aug 2025 14:12:55 -0300
From: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
To: airlied@...il.com,
	amergnat@...libre.com,
	andrew+netdev@...n.ch,
	andrew-ct.chen@...iatek.com,
	angelogioacchino.delregno@...labora.com,
	ariel.dalessandro@...labora.com,
	broonie@...nel.org,
	chunkuang.hu@...nel.org,
	ck.hu@...iatek.com,
	conor+dt@...nel.org,
	davem@...emloft.net,
	dmitry.torokhov@...il.com,
	edumazet@...gle.com,
	flora.fu@...iatek.com,
	houlong.wei@...iatek.com,
	jeesw@...fas.com,
	jmassot@...labora.com,
	kernel@...labora.com,
	krzk+dt@...nel.org,
	kuba@...nel.org,
	kyrie.wu@...iatek.corp-partner.google.com,
	lgirdwood@...il.com,
	linus.walleij@...aro.org,
	louisalexis.eyraud@...labora.com,
	maarten.lankhorst@...ux.intel.com,
	matthias.bgg@...il.com,
	mchehab@...nel.org,
	minghsiu.tsai@...iatek.com,
	mripard@...nel.org,
	p.zabel@...gutronix.de,
	pabeni@...hat.com,
	robh@...nel.org,
	sean.wang@...nel.org,
	simona@...ll.ch,
	support.opensource@...semi.com,
	tiffany.lin@...iatek.com,
	tzimmermann@...e.de,
	yunfei.dong@...iatek.com
Cc: devicetree@...r.kernel.org,
	dri-devel@...ts.freedesktop.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-clk@...r.kernel.org,
	linux-gpio@...r.kernel.org,
	linux-input@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-media@...r.kernel.org,
	linux-mediatek@...ts.infradead.org,
	linux-sound@...r.kernel.org,
	netdev@...r.kernel.org
Subject: [PATCH v1 07/14] dt-bindings: display: mediatek,ufoe: Add mediatek,gce-client-reg property

Current, the DT bindings for Mediatek UFOe (Unified Frame Optimization
engine) is missing the mediatek,gce-client-reg property. Add it and
update the example as well.

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
---
 .../bindings/display/mediatek/mediatek,ufoe.yaml      | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
index 61a5e22effbf2..ecb4c0359fec3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -64,6 +64,14 @@ properties:
       - port@0
       - port@1
 
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -77,7 +85,9 @@ examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
     #include <dt-bindings/power/mt8173-power.h>
+
     soc {
         #address-cells = <2>;
         #size-cells = <2>;
@@ -88,5 +98,6 @@ examples:
             interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_DISP_UFOE>;
+            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
         };
     };
-- 
2.50.1


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ