netdev - Re: Aquantia PHY in OCSGMII mode?

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Message-ID: <aK7Ep7Khdw58hyA0@FUE-ALEWI-WINX>
Date: Wed, 27 Aug 2025 10:41:11 +0200
From: Alexander Wilhelm <alexander.wilhelm@...termo.com>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: "Russell King (Oracle)" <linux@...linux.org.uk>,
        Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: Aquantia PHY in OCSGMII mode?

Am Wed, Aug 27, 2025 at 10:31:20AM +0300 schrieb Vladimir Oltean:
> Hi Alexander,
> 
> On Wed, Aug 27, 2025 at 07:57:28AM +0200, Alexander Wilhelm wrote:
> > Hi Vladimir,
> > 
> > One of our hardware engineers has looked into the issue with the 100M link and
> > found the following: the Aquantia AQR115 always uses 2500BASE-X (GMII) on the
> > host side. For both 1G and 100M operation, it enables pause rate adaptation.
> > However, our MAC only applies rate adaptation for 1G links. For 100M, it uses a
> > 10x symbol replication instead.
> > 
> > We’re exploring a workaround where the MAC is configured to believe it’s
> > operating at 1G, so it continues using pause rate adaptation, since flow control
> 
> Why at 1G and not at 2.5G?

Good point. Actually it is 2.5G, but the source code does not really
differentiate between them. All register configurations are the same for both 1G
and 2.5G.
[...]

> To be crystal clear, are you talking about the T1023 FMan mEMAC as being
> the one which at 100M uses 10x symbol replication? Because the AQR115
> PHY also contains a MAC block inside - this is what provides the MACsec
> and rate adaptation functionality.

Exactly that is what our hardware engineer measured.

> And if so, I don't know _how_ can that be - in mainline there is no code
> that would reconfigure the SerDes lane from 2500base-x to SGMII. These
> use different baud rates, so the lane would need to be moved to a
> different PLL which provides the required clock net. Or are you using a
> different kernel code base where this logic exists?

That is the problem I'm trying to understand. I've also not seen any code that
changes that. I'm using OpenWRT v24.10.0 with default kernel v6.6.73. The only
patches applied are the ones you've provided to me.

> Also, I don't understand _why_ would the FMan mEMAC change its protocol
> from 2500base-x to SGMII. It certainly doesn't do that by itself.
> Rate adaptation is handled by phylink (phylink_link_up() sets rx_pause
> unconditionally to true when in RATE_MATCH_PAUSE mode), and the MAC
> should be kept in the same configuration for different media-side speeds.
> 
> Could you print phy_modes(state->interface) in memac_mac_config(), as
> well as phy_modes(interface), speed, duplex, tx_pause, rx_pause in
> memac_link_up()? This is to confirm that the mEMAC configuration is
> identical when the PHY links at 1G and 100M.

Sure. I set speed on host connected to the DUT. Here are the logs:

Started with 2.5G:

    fsl_dpaa_mac: [DEBUG] <memac_mac_config> called
    fsl_dpaa_mac: [DEBUG] * phy_modes(state->interface): 2500base-x
    fsl_dpaa_mac: [DEBUG] <memac_link_up> called
    fsl_dpaa_mac: [DEBUG] * mode: 0
    fsl_dpaa_mac: [DEBUG] * phy_mode(interface): 2500base-x
    fsl_dpaa_mac: [DEBUG] * memac_if_mode: 00000002 (IF_MODE_GMII)
    fsl_dpaa_mac: [DEBUG] * speed: 2500
    fsl_dpaa_mac: [DEBUG] * duplex: 1
    fsl_dpaa_mac: [DEBUG] * tx_pause: 1
    fsl_dpaa_mac: [DEBUG] * rx_pause: 1

Set to 1G:

    fsl_dpaa_mac: [DEBUG] <memac_link_down> called
    fsl_dpaa_mac: [DEBUG] <memac_link_up> called
    fsl_dpaa_mac: [DEBUG] * mode: 0
    fsl_dpaa_mac: [DEBUG] * phy_mode(interface): 2500base-x
    fsl_dpaa_mac: [DEBUG] * memac_if_mode: 00000002 (IF_MODE_GMII)
    fsl_dpaa_mac: [DEBUG] * speed: 2500
    fsl_dpaa_mac: [DEBUG] * duplex: 1
    fsl_dpaa_mac: [DEBUG] * tx_pause: 1
    fsl_dpaa_mac: [DEBUG] * rx_pause: 1

Set to 100M:

    fsl_dpaa_mac: [DEBUG] <memac_link_down> called
    fsl_dpaa_mac: [DEBUG] <memac_link_up> called
    fsl_dpaa_mac: [DEBUG] * mode: 0
    fsl_dpaa_mac: [DEBUG] * phy_mode(interface): 2500base-x
    fsl_dpaa_mac: [DEBUG] * memac_if_mode: 00000002 (IF_MODE_GMII)
    fsl_dpaa_mac: [DEBUG] * speed: 2500
    fsl_dpaa_mac: [DEBUG] * duplex: 1
    fsl_dpaa_mac: [DEBUG] * tx_pause: 1
    fsl_dpaa_mac: [DEBUG] * rx_pause: 1


Best regards
Alexander Wilhelm