| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <uvdrqzpqc5vki6sh5f7phktuk47egtmfuw3jjvoakrbyhqxwvt@obao75mbrtti>
Date: Wed, 27 Aug 2025 18:06:04 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Wasim Nazir <wasim.nazir@....qualcomm.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Richard Cochran <richardcochran@...il.com>,
kernel@....qualcomm.com, linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, netdev@...r.kernel.org,
Viken Dadhaniya <viken.dadhaniya@....qualcomm.com>, Sushrut Shree Trivedi <quic_sushruts@...cinc.com>,
Nirmesh Kumar Singh <quic_nkumarsi@...cinc.com>, Krishna Kurapati <krishna.kurapati@....qualcomm.com>,
Mohd Ayaan Anwar <quic_mohdayaa@...cinc.com>, Dikshita Agarwal <quic_dikshita@...cinc.com>,
Monish Chunara <quic_mchunara@...cinc.com>, Vishal Kumar Pal <quic_vispal@...cinc.com>
Subject: Re: [PATCH 3/5] arm64: dts: qcom: lemans-evk: Extend peripheral and
subsystem support
On Tue, Aug 26, 2025 at 11:51:02PM +0530, Wasim Nazir wrote:
> Enhance the Qualcomm Lemans EVK board file to support essential
> peripherals and improve overall hardware capabilities, as
> outlined below:
> - Enable GPI (Generic Peripheral Interface) DMA-0/1/2 and QUPv3-0/2
> controllers to facilitate DMA and peripheral communication.
> - Add support for PCIe-0/1, including required regulators and PHYs,
> to enable high-speed external device connectivity.
> - Integrate the TCA9534 I/O expander via I2C to provide 8 additional
> GPIO lines for extended I/O functionality.
> - Enable the USB0 controller in device mode to support USB peripheral
> operations.
> - Activate remoteproc subsystems for supported DSPs such as Audio DSP,
> Compute DSP-0/1 and Generic DSP-0/1, along with their corresponding
> firmware.
> - Configure nvmem-layout on the I2C EEPROM to store data for Ethernet
> and other consumers.
> - Enable the QCA8081 2.5G Ethernet PHY on port-0 and expose the
> Ethernet MAC address via nvmem for network configuration.
> It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY.
> - Add support for the Iris video decoder, including the required
> firmware, to enable video decoding capabilities.
> - Enable SD-card slot on SDHC.
I know I asked for you to lump things together in the initial
contribution to provide as much features as possible in that initial
patch, but now that is in place and this patch really is a bunch of
independent logical changes and this commit message reads much more like
a cover letter...
>
> Co-developed-by: Viken Dadhaniya <viken.dadhaniya@....qualcomm.com>
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@....qualcomm.com>
> Co-developed-by: Sushrut Shree Trivedi <quic_sushruts@...cinc.com>
> Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@...cinc.com>
> Co-developed-by: Nirmesh Kumar Singh <quic_nkumarsi@...cinc.com>
> Signed-off-by: Nirmesh Kumar Singh <quic_nkumarsi@...cinc.com>
> Co-developed-by: Krishna Kurapati <krishna.kurapati@....qualcomm.com>
> Signed-off-by: Krishna Kurapati <krishna.kurapati@....qualcomm.com>
> Co-developed-by: Mohd Ayaan Anwar <quic_mohdayaa@...cinc.com>
> Signed-off-by: Mohd Ayaan Anwar <quic_mohdayaa@...cinc.com>
> Co-developed-by: Dikshita Agarwal <quic_dikshita@...cinc.com>
> Signed-off-by: Dikshita Agarwal <quic_dikshita@...cinc.com>
> Co-developed-by: Monish Chunara <quic_mchunara@...cinc.com>
> Signed-off-by: Monish Chunara <quic_mchunara@...cinc.com>
> Co-developed-by: Vishal Kumar Pal <quic_vispal@...cinc.com>
> Signed-off-by: Vishal Kumar Pal <quic_vispal@...cinc.com>
> Signed-off-by: Wasim Nazir <wasim.nazir@....qualcomm.com>
And I don't think you all wrote this patch, you probably all wrote
individual pieces and then one of you created the actual patch?
The important part is that we don't want 9 different patch series
floating around with unmet dependencies and relying on me to try to
stitch them together.
But if you could do what you did for patch 2, 4, and 5 for logical
chunks of this change, that would be excellent (i.e. you collect the
individual patches, you add your signed-off-by, and you send them all
together).
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/lemans-evk.dts | 387 ++++++++++++++++++++++++++++++++
> 1 file changed, 387 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
> index 9e415012140b..642b66c4ad1e 100644
> --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
> @@ -16,7 +16,10 @@ / {
> compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
>
> aliases {
> + ethernet0 = ðernet0;
> + mmc1 = &sdhc;
> serial0 = &uart10;
> + serial1 = &uart17;
> };
>
> chosen {
> @@ -46,6 +49,30 @@ edp1_connector_in: endpoint {
> };
> };
> };
> +
> + vmmc_sdc: regulator-vmmc-sdc {
> + compatible = "regulator-fixed";
> + regulator-name = "vmmc_sdc";
> +
> + regulator-min-microvolt = <2950000>;
> + regulator-max-microvolt = <2950000>;
> + };
> +
> + vreg_sdc: regulator-vreg-sdc {
> + compatible = "regulator-gpio";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-name = "vreg_sdc";
> + regulator-type = "voltage";
> +
> + startup-delay-us = <100>;
> +
> + gpios = <&expander1 7 GPIO_ACTIVE_HIGH>;
> +
> + states = <1800000 0x1
> + 2950000 0x0>;
> + };
> };
>
> &apps_rsc {
> @@ -277,6 +304,161 @@ vreg_l8e: ldo8 {
> };
> };
>
> +ðernet0 {
> + phy-handle = <&hsgmii_phy0>;
> + phy-mode = "2500base-x";
> +
> + pinctrl-0 = <ðernet0_default>;
> + pinctrl-names = "default";
> +
> + snps,mtl-rx-config = <&mtl_rx_setup>;
> + snps,mtl-tx-config = <&mtl_tx_setup>;
> + snps,ps-speed = <1000>;
> +
> + nvmem-cells = <&mac_addr0>;
> + nvmem-cell-names = "mac-address";
> +
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hsgmii_phy0: ethernet-phy@1c {
> + compatible = "ethernet-phy-id004d.d101";
> + reg = <0x1c>;
> + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <11000>;
> + reset-deassert-us = <70000>;
> + };
> + };
> +
> + mtl_rx_setup: rx-queues-config {
> + snps,rx-queues-to-use = <4>;
> + snps,rx-sched-sp;
> +
> + queue0 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x0>;
> + snps,route-up;
> + snps,priority = <0x1>;
> + };
> +
> + queue1 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x1>;
> + snps,route-ptp;
> + };
> +
> + queue2 {
> + snps,avb-algorithm;
> + snps,map-to-dma-channel = <0x2>;
> + snps,route-avcp;
> + };
> +
> + queue3 {
> + snps,avb-algorithm;
> + snps,map-to-dma-channel = <0x3>;
> + snps,priority = <0xc>;
> + };
> + };
> +
> + mtl_tx_setup: tx-queues-config {
> + snps,tx-queues-to-use = <4>;
> +
> + queue0 {
> + snps,dcb-algorithm;
> + };
> +
> + queue1 {
> + snps,dcb-algorithm;
> + };
> +
> + queue2 {
> + snps,avb-algorithm;
> + snps,send_slope = <0x1000>;
> + snps,idle_slope = <0x1000>;
> + snps,high_credit = <0x3e800>;
> + snps,low_credit = <0xffc18000>;
> + };
> +
> + queue3 {
> + snps,avb-algorithm;
> + snps,send_slope = <0x1000>;
> + snps,idle_slope = <0x1000>;
> + snps,high_credit = <0x3e800>;
> + snps,low_credit = <0xffc18000>;
> + };
> + };
> +};
> +
> +&gpi_dma0 {
> + status = "okay";
> +};
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
> +
> +&gpi_dma2 {
> + status = "okay";
> +};
> +
> +&i2c18 {
> + status = "okay";
> +
> + expander0: pca953x@38 {
> + compatible = "ti,tca9538";
> + #gpio-cells = <2>;
> + gpio-controller;
> + reg = <0x38>;
> + };
> +
> + expander1: pca953x@39 {
> + compatible = "ti,tca9538";
> + #gpio-cells = <2>;
> + gpio-controller;
> + reg = <0x39>;
> + };
> +
> + expander2: pca953x@3a {
> + compatible = "ti,tca9538";
> + #gpio-cells = <2>;
> + gpio-controller;
> + reg = <0x3a>;
> + };
> +
> + expander3: pca953x@3b {
> + compatible = "ti,tca9538";
> + #gpio-cells = <2>;
> + gpio-controller;
> + reg = <0x3b>;
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c256";
> + reg = <0x50>;
> + pagesize = <64>;
> +
> + nvmem-layout {
> + compatible = "fixed-layout";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + mac_addr0: mac-addr@0 {
> + reg = <0x0 0x6>;
> + };
> + };
> + };
> +};
> +
> +&iris {
> + firmware-name = "qcom/vpu/vpu30_p4_s6.mbn";
> +
> + status = "okay";
> +};
> +
> &mdss0 {
> status = "okay";
> };
> @@ -323,14 +505,196 @@ &mdss0_dp1_phy {
> status = "okay";
> };
>
> +&pcie0 {
> + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_default_state>;
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l5a>;
> + vdda-pll-supply = <&vreg_l1c>;
> +
> + status = "okay";
> +};
> +
> +&pcie1 {
> + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_default_state>;
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + vdda-phy-supply = <&vreg_l5a>;
> + vdda-pll-supply = <&vreg_l1c>;
> +
> + status = "okay";
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> &qupv3_id_1 {
> status = "okay";
> };
>
> +&qupv3_id_2 {
> + status = "okay";
> +};
> +
> +&remoteproc_adsp {
> + firmware-name = "qcom/sa8775p/adsp.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp0 {
> + firmware-name = "qcom/sa8775p/cdsp0.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp1 {
> + firmware-name = "qcom/sa8775p/cdsp1.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_gpdsp0 {
> + firmware-name = "qcom/sa8775p/gpdsp0.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_gpdsp1 {
> + firmware-name = "qcom/sa8775p/gpdsp1.mbn";
> +
> + status = "okay";
> +};
> +
> +&sdhc {
> + vmmc-supply = <&vmmc_sdc>;
> + vqmmc-supply = <&vreg_sdc>;
> +
> + pinctrl-0 = <&sdc_default>, <&sd_cd>;
> + pinctrl-1 = <&sdc_sleep>, <&sd_cd>;
> + pinctrl-names = "default", "sleep";
> +
> + power-domains = <&rpmhpd SA8775P_CX>;
> + operating-points-v2 = <&sdhc_opp_table>;
> +
> + cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +
> + sdhc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1800000 400000>;
> + opp-avg-kBps = <100000 0>;
> + };
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <5400000 1600000>;
> + opp-avg-kBps = <390000 0>;
> + };
> + };
> +};
> +
> +&serdes0 {
> + phy-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> &sleep_clk {
> clock-frequency = <32768>;
> };
>
> +&tlmm {
> + ethernet0_default: ethernet0-default-state {
> + ethernet0_mdc: ethernet0-mdc-pins {
> + pins = "gpio8";
> + function = "emac0_mdc";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> +
> + ethernet0_mdio: ethernet0-mdio-pins {
> + pins = "gpio9";
> + function = "emac0_mdio";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie0_default_state: pcie0-default-state {
> + clkreq-pins {
> + pins = "gpio1";
> + function = "pcie0_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-pins {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-pins {
> + pins = "gpio0";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_default_state: pcie1-default-state {
> + clkreq-pins {
> + pins = "gpio3";
> + function = "pcie1_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-pins {
> + pins = "gpio4";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-pins {
> + pins = "gpio5";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + sd_cd: sd-cd-state {
> + pins = "gpio36";
> + function = "gpio";
> + bias-pull-up;
> + };
> +};
> +
> &uart10 {
> compatible = "qcom,geni-debug-uart";
> pinctrl-0 = <&qup_uart10_default>;
> @@ -356,6 +720,29 @@ &ufs_mem_phy {
> status = "okay";
> };
>
> +&usb_0 {
> + status = "okay";
> +};
> +
> +&usb_0_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_0_hsphy {
> + vdda-pll-supply = <&vreg_l7a>;
> + vdda18-supply = <&vreg_l6c>;
> + vdda33-supply = <&vreg_l9a>;
> +
> + status = "okay";
> +};
> +
> +&usb_0_qmpphy {
> + vdda-phy-supply = <&vreg_l1c>;
> + vdda-pll-supply = <&vreg_l7a>;
> +
> + status = "okay";
> +};
> +
> &xo_board_clk {
> clock-frequency = <38400000>;
> };
>
> --
> 2.51.0
>
Powered by blists - more mailing lists