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Message-ID: <20250828-qcom_ipq5424_nsscc-v4-0-cb913b205bcb@quicinc.com>
Date: Thu, 28 Aug 2025 18:32:13 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Varadarajan
Narayanan" <quic_varada@...cinc.com>,
Georgi Djakov <djakov@...nel.org>, "Rob
Herring" <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
"Conor
Dooley" <conor+dt@...nel.org>,
Anusha Rao <quic_anusha@...cinc.com>,
"Manikanta Mylavarapu" <quic_mmanikan@...cinc.com>,
Devi Priya
<quic_devipriy@...cinc.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"Richard
Cochran" <richardcochran@...il.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>,
<netdev@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<quic_kkumarcs@...cinc.com>, <quic_linchen@...cinc.com>,
<quic_leiwei@...cinc.com>, <quic_pavir@...cinc.com>,
<quic_suruchia@...cinc.com>, Luo Jie
<quic_luoj@...cinc.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH v4 00/10] Add Network Subsystem (NSS) clock controller
support for IPQ5424 SoC
The NSS clock controller on the IPQ5424 SoC provides clocks and resets
to the networking related hardware blocks such as the Packet Processing
Engine (PPE) and UNIPHY (PCS). Its parent clocks are sourced from the
GCC, CMN PLL, and UNIPHY blocks.
Additionally, register the gpll0_out_aux GCC clock, which serves as one
of the parent clocks for some of the NSS clocks.
The NSS NoC clocks are also enabled to use the icc-clk framework, enabling
the creation of interconnect paths for the network subsystem’s connections
with these NoCs.
The NSS clock controller receives its input clocks from the CMN PLL outputs.
The related patch series which adds support for IPQ5424 SoC in the CMN PLL
driver is listed below.
https://lore.kernel.org/all/20250610-qcom_ipq5424_cmnpll-v3-0-ceada8165645@quicinc.com/
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
Changes in v4:
- Add new, generic clock names "nss" and "ppe" in DT bindings to support
the newer SoC such as IPQ5424 SoC, while retaining existing clock names
for IPQ9574.
- Register all necessary NoC clocks as interconnect paths.
- Separate the fix for correcting icc_first_node_id into its own patch.
- Separate the fix requiring the "#interconnect-cells" property for NSS
clock controller node.
- Update commit titles from "clock:" to "clk:" for consistency.
- Update copyright to remove year as per guidelines in all driver files.
- Remove the Acked-by tag from the "Add Qualcomm IPQ5424 NSSNOC IDs" patch"
as the new NOC IDs are added.
- Link to v3: https://lore.kernel.org/r/20250710-qcom_ipq5424_nsscc-v3-0-f149dc461212@quicinc.com
Changes in v3:
- Remove frequency suffix from clock names for PPE and NSS clocks in
IPQ9574 DT binding and DTS.
- Update IPQ5424 DT bindings and DTS to as per new PPE and NSS clock names.
- Expand the register region of IPQ5424 NSSCC to utilize the entire 0x100_000
address range, ensuring inclusion of the wrapper region.
- Collect the reviewed-by tags.
- Link to v2: https://lore.kernel.org/r/20250627-qcom_ipq5424_nsscc-v2-0-8d392f65102a@quicinc.com
Changes in v2:
- Add new, separate clock names "nss" and "ppe" in dtbindings to support
the IPQ5424 SoC.
- Wrap the commit message body at 75 columns.
- Fix the indentation issue in the `IPQ_NSSCC_5424` Kconfig entry.
- Enhance the commit message for the defconfig patch to clarify the requirement
for enabling `IPQ_NSSCC_5424`.
- Link to v1: https://lore.kernel.org/r/20250617-qcom_ipq5424_nsscc-v1-0-4dc2d6b3cdfc@quicinc.com
---
Luo Jie (10):
clk: qcom: gcc-ipq5424: Correct the icc_first_node_id
dt-bindings: interconnect: Add Qualcomm IPQ5424 NSSNOC IDs
clk: qcom: gcc-ipq5424: Enable NSS NoC clocks to use icc-clk
dt-bindings: clock: gcc-ipq5424: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock
dt-bindings: clock: Add required "interconnect-cells" property
dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC
clk: qcom: Add NSS clock controller driver for IPQ5424
arm64: dts: qcom: ipq5424: Add NSS clock controller node
arm64: defconfig: Build NSS clock controller driver for IPQ5424
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 64 +-
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 32 +-
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5424.c | 28 +-
drivers/clk/qcom/nsscc-ipq5424.c | 1340 ++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq5424-gcc.h | 3 +-
include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 +
include/dt-bindings/interconnect/qcom,ipq5424.h | 33 +
include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +
11 files changed, 1613 insertions(+), 11 deletions(-)
---
base-commit: 8cd53fb40a304576fa86ba985f3045d5c55b0ae3
change-id: 20250828-qcom_ipq5424_nsscc-d9f4eaf21795
Best regards,
--
Luo Jie <quic_luoj@...cinc.com>
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