[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250828-qcom_ipq5424_nsscc-v4-2-cb913b205bcb@quicinc.com>
Date: Thu, 28 Aug 2025 18:32:15 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Varadarajan
Narayanan" <quic_varada@...cinc.com>,
Georgi Djakov <djakov@...nel.org>, "Rob
Herring" <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
"Conor
Dooley" <conor+dt@...nel.org>,
Anusha Rao <quic_anusha@...cinc.com>,
"Manikanta Mylavarapu" <quic_mmanikan@...cinc.com>,
Devi Priya
<quic_devipriy@...cinc.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"Richard
Cochran" <richardcochran@...il.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>,
<netdev@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<quic_kkumarcs@...cinc.com>, <quic_linchen@...cinc.com>,
<quic_leiwei@...cinc.com>, <quic_pavir@...cinc.com>,
<quic_suruchia@...cinc.com>, Luo Jie
<quic_luoj@...cinc.com>
Subject: [PATCH v4 02/10] dt-bindings: interconnect: Add Qualcomm IPQ5424
NSSNOC IDs
Add the NSSNOC master/slave ids for Qualcomm IPQ5424 network subsystem
(NSS) hardware blocks. These will be used by the gcc-ipq5424 driver
that provides the interconnect services by using the icc-clk framework.
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
include/dt-bindings/interconnect/qcom,ipq5424.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index afd7e0683a24..c5e0dec0b300 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -20,6 +20,26 @@
#define SLAVE_CNOC_PCIE3 15
#define MASTER_CNOC_USB 16
#define SLAVE_CNOC_USB 17
+#define MASTER_NSSNOC_NSSCC 18
+#define SLAVE_NSSNOC_NSSCC 19
+#define MASTER_NSSNOC_SNOC_0 20
+#define SLAVE_NSSNOC_SNOC_0 21
+#define MASTER_NSSNOC_SNOC_1 22
+#define SLAVE_NSSNOC_SNOC_1 23
+#define MASTER_NSSNOC_PCNOC_1 24
+#define SLAVE_NSSNOC_PCNOC_1 25
+#define MASTER_NSSNOC_QOSGEN_REF 26
+#define SLAVE_NSSNOC_QOSGEN_REF 27
+#define MASTER_NSSNOC_TIMEOUT_REF 28
+#define SLAVE_NSSNOC_TIMEOUT_REF 29
+#define MASTER_NSSNOC_XO_DCD 30
+#define SLAVE_NSSNOC_XO_DCD 31
+#define MASTER_NSSNOC_ATB 32
+#define SLAVE_NSSNOC_ATB 33
+#define MASTER_CNOC_LPASS_CFG 34
+#define SLAVE_CNOC_LPASS_CFG 35
+#define MASTER_SNOC_LPASS 36
+#define SLAVE_SNOC_LPASS 37
#define MASTER_CPU 0
#define SLAVE_L3 1
--
2.34.1
Powered by blists - more mailing lists