netdev - RE: [PATCH net-next v3 2/2] net: maxlinear: Add support for MxL LGM SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <PH7PR19MB56366632D5609B0B51FE8939B406A@PH7PR19MB5636.namprd19.prod.outlook.com>
Date: Tue, 2 Sep 2025 10:39:38 +0000
From: Jack Ping Chng <jchng@...linear.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"davem@...emloft.net" <davem@...emloft.net>, "andrew+netdev@...n.ch"
	<andrew+netdev@...n.ch>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>, Yi xin Zhu
	<yzhu@...linear.com>, Suresh Nagaraj <sureshnagaraj@...linear.com>
Subject: RE: [PATCH net-next v3 2/2] net: maxlinear: Add support for MxL LGM
 SoC

On Mon, 1 Sep 2025 15:11:08 +0200
Andrew Lunn <andrew@...n.ch> wrote:

> On Mon, Sep 01, 2025 at 09:38:44AM +0000, Jack Ping Chng wrote:
> > Hi Andrew,
> >
> > On Fri, 29 Aug 2025 22:24:06 +0200
> > Andrew Lunn <andrew@...n.ch> wrote:
> >
> > > > +This document describes the Linux driver for the MaxLinear Network Processor
> > > > +(NP), a high-performance controller supporting multiple MACs and
> > > > +advanced packet processing capabilities.
> > > > +
> > > > +The MaxLinear Network processor integrates programmable hardware accelerators
> > > > +for tasks such as Layer 2, 3, 4 forwarding, flow steering, and traffic shaping.
> > >
> > > By L2 and L3, do you mean this device can bridge and route frames
> > > between ports? So it is actually a switch?
> >
> > Yes, the SoC does support packet acceleration.
> > However, this patch series primarily focuses on the host interface to deliver packets to the CPU,
> > where bridging and routing are handled within the network stack.
> 
> Linux has two ways to support a switch. Pure switchdev, or switchdev +
> DSA. Which to use depends on the architecture of the device. I would
> like to check now, before you get too far, what the hardware
> architecture is.

Hi Andrew,

Thank you for your valuable feedback.

The switch core hardware block is part of the MaxLinear Lightning
Mountain (LGM) SoC, which integrates Ethernet XGMACs for connectivity
with external PHY devices via PCS. 
At initialization, we configure the switch core ports to enable only
Layer 2 frame forwarding between the CPU (Host Interface) port and the
Ethernet ports.
L2/FDB learning and forwarding will not be enabled for any port.
The CPU port facilitates packet transfers between the Ethernet ports
and the CPU within the SoC using DMA. All forwarding and routing
logic is handled in the Linux network stack. 

LGM SoC also has a separate HW offload engine for packet routing and
bridging per flow.  This is not within the scope of this patch series.

> Are there any public available block diagrams of this device?

We will  update the documentation accordingly in the upcoming version.
Please find the packet flow at a high level below:
Rx: 
PHY -> Switch Core XGMAC -> Host Interface Port -> DMA Rx -> CPU 
Tx:
CPU -> DMA Tx -> Host Interface Port -> Switch Core XGMAC -> PHY

> How does the host direct a frame out a specific port of the switch?

In the TX direction, there is a predefined mapping between the Ethernet
interface and the corresponding destination switch port. 
The Ethernet driver communicates this mapping to the DMA driver, 
which then embeds it into the DMA descriptor as sideband information. 
This ensures that the data is forwarded correctly through the switch fabric

> How does the host know which port a frame came in on?

On the RX side, the source switch port  is mapped to a specific DMA Rx
channel. The DMA Rx descriptor also carries the ingress port as
sideband information.
Either of these methods can be used to determine the source switch port.

Best regards,
Jack