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Message-ID: <021e970a-f606-4702-9f0e-b4b0576bc5d6@lunn.ch>
Date: Thu, 4 Sep 2025 22:37:49 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Clément Léger <clement.leger@...tlin.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Philipp Zabel <p.zabel@...gutronix.de>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode
mask SoC-specific
On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Move the hardcoded switch mode mask definition into the SoC-specific
> miic_of_data structure. This allows each SoC to define its own mask
> value rather than relying on a single fixed constant. For RZ/N1 the
> mask remains GENMASK(4, 0).
>
> This is in preparation for adding support for RZ/T2H, where the
> switch mode mask is GENMASK(2, 0).
> -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
> miic_reg_writel(miic, MIIC_MODCTRL,
> - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
_ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
this __ffs() is pointless.
You might however want to add a comment that this assumption is being
made.
Andrew
---
pw-bot: cr
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