netdev - Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

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Message-ID: <CA+V-a8unTSqBottT7uDGkSxDYpRAYnpZvRC2RKsm9M0rw09iFQ@mail.gmail.com>
Date: Fri, 5 Sep 2025 11:01:06 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Andrew Lunn <andrew@...n.ch>, Clément Léger <clement.leger@...tlin.com>, 
	Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Geert Uytterhoeven <geert+renesas@...der.be>, 
	Magnus Damm <magnus.damm@...il.com>, Wolfram Sang <wsa+renesas@...g-engineering.com>, 
	linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode
 mask SoC-specific

Hi Geert,

On Fri, Sep 5, 2025 at 8:02 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Andrew,
>
> On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@...n.ch> wrote:
> > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Move the hardcoded switch mode mask definition into the SoC-specific
> > > miic_of_data structure. This allows each SoC to define its own mask
> > > value rather than relying on a single fixed constant. For RZ/N1 the
> > > mask remains GENMASK(4, 0).
> > >
> > > This is in preparation for adding support for RZ/T2H, where the
> > > switch mode mask is GENMASK(2, 0).
> >
> > > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
> >
> > >       miic_reg_writel(miic, MIIC_MODCTRL,
> > > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
> >
> > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> > this __ffs() is pointless.
> >
> > You might however want to add a comment that this assumption is being
> > made.
>
> I guess Prabhakar did it this way to make it easier to find
> candidates for a future conversion to field_prep(), if this ever becomes
> available[1].
>
> [1] "[PATCH v3 0/4] Non-const bitfield helpers"
>     https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be
>
Ah thanks, I wanted to explore this and add a new macro but I thought
it might delay this series so I dropped it. Hopefully your series will
get in soon.

Cheers,
Prabhakar