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Message-ID: <b4c0f677-a97a-4076-a1d6-238854236ec9@collabora.com>
Date: Fri, 12 Sep 2025 10:11:31 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Ariel D'Alessandro <ariel.dalessandro@...labora.com>, airlied@...il.com,
amergnat@...libre.com, andrew+netdev@...n.ch, andrew-ct.chen@...iatek.com,
broonie@...nel.org, chunkuang.hu@...nel.org, conor+dt@...nel.org,
davem@...emloft.net, dmitry.torokhov@...il.com, edumazet@...gle.com,
flora.fu@...iatek.com, heiko@...ech.de, houlong.wei@...iatek.com,
jeesw@...fas.com, kernel@...labora.com, krzk+dt@...nel.org, kuba@...nel.org,
lgirdwood@...il.com, linus.walleij@...aro.org,
louisalexis.eyraud@...labora.com, luiz.dentz@...il.com,
maarten.lankhorst@...ux.intel.com, marcel@...tmann.org,
matthias.bgg@...il.com, mchehab@...nel.org, minghsiu.tsai@...iatek.com,
mripard@...nel.org, p.zabel@...gutronix.de, pabeni@...hat.com,
robh@...nel.org, sean.wang@...nel.org, simona@...ll.ch,
support.opensource@...semi.com, tiffany.lin@...iatek.com,
tzimmermann@...e.de, yunfei.dong@...iatek.com
Cc: devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org, linux-bluetooth@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-input@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-media@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-sound@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH v2 01/12] dt-bindings: media: Convert MediaTek mt8173-mdp
bindings to DT schema
Il 11/09/25 17:09, Ariel D'Alessandro ha scritto:
> Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
> Path to a DT schema.
>
> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
> .../bindings/media/mediatek-mdp.txt | 95 ----------
> 2 files changed, 169 insertions(+), 95 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> new file mode 100644
> index 0000000000000..8ca33a733c478
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 Media Data Path
> +
> +maintainers:
> + - Ariel D'Alessandro <ariel.dalessandro@...labora.com>
> +
> +description:
> + Media Data Path is used for scaling and color space conversion.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-rsz
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
> + - items:
> + - const: mediatek,mt8173-mdp-rdma
> + - const: mediatek,mt8173-mdp
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + power-domains:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + mediatek,vpu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
> + image processing.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp-rdma
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> + - description: Mutex clock
> + else:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
> + then:
> + required:
> + - iommus
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp
> + then:
> + required:
> + - mediatek,vpu
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/memory/mt8173-larb-port.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdp_rdma0: rdma@...01000 {
> + compatible = "mediatek,mt8173-mdp-rdma",
> + "mediatek,mt8173-mdp";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,vpu = <&vpu>;
> + };
> +
> + mdp_rdma1: rdma@...02000 {
> + compatible = "mediatek,mt8173-mdp-rdma";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> + };
> +
> + mdp_rsz0: rsz@...03000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14003000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz1: rsz@...04000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14004000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz2: rsz@...05000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ2>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_wdma0: wdma@...06000 {
> + compatible = "mediatek,mt8173-mdp-wdma";
> + reg = <0 0x14006000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA>;
> + };
> +
> + mdp_wrot0: wrot@...07000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14007000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + };
> +
> + mdp_wrot1: wrot@...08000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14008000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT1>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT1>;
> + };
> + };
> +
> +...
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